Datasheet

 2011-2012 Microchip Technology Inc. DS75018C-page 233
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 19-2: ADSTAT: ADC STATUS REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/C-0, HS U-0 U-0 R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS
—P6RDY — —P3RDY
(1)
P2RDY
(2)
P1RDY P0RDY
bit 7 bit 0
Legend: C = Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6 P6RDY: Conversion Data for Pair 6 Ready bit
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
bit 5-4 Unimplemented: Read as ‘0’
bit 3 P3RDY: Conversion Data for Pair 3 Ready bit
(1)
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
bit 2 P2RDY: Conversion Data for Pair 3 Ready bit
(2)
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
bit 1 P1RDY: Conversion Data for Pair 1 Ready bit
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
bit 0 P0RDY: Conversion Data for Pair 0 Ready bit
Bit is set when data is ready in buffer, cleared when a ‘0’ is written to this bit.
Note 1: This bit is not implemented in dsPIC33FJ06GS102A/202A devices.
2: This bit is not implemented in dsPIC33FJ06GS001/101A devices.