Datasheet

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
DS75018C-page 232  2011-2012 Microchip Technology Inc.
bit 8 FORM: Data Output Format bit
(1)
1 = Fractional (DOUT = dddd dddd dd00 0000)
0 = Integer (D
OUT = 0000 00dd dddd dddd)
bit 7 EIE: Early Interrupt Enable bit
(1)
1 = Interrupt is generated after first conversion is completed
0 = Interrupt is generated after second conversion is completed
bit 6 ORDER: Conversion Order bit
(1)
1 = Odd numbered analog input is converted first, followed by conversion of even numbered input
0 = Even numbered analog input is converted first, followed by conversion of odd numbered input
bit 5 SEQSAMP: Sequential Sample Enable bit
(1)
1 = Shared Sample-and-Hold (S&H) circuit is sampled at the start of the second conversion if
ORDER = 0. If ORDER = 1, then the shared S&H is sampled at the start of the first conversion.
0 = Shared S&H is sampled at the same time the dedicated S&H is sampled if the shared S&H is not
currently busy with an existing conversion process. If the shared S&H is busy at the time the
dedicated S&H is sampled, then the shared S&H will sample at the start of the new conversion
cycle.
bit 4 ASYNCSAMP: Asynchronous Dedicated S&H Sampling Enable bit
(1)
1 = The dedicated S&H is constantly sampling and then terminates sampling as soon as the trigger
pulse is detected
0 = The dedicated S&H starts sampling when the trigger event is detected and completes the sampling
process in two ADC clock cycles
bit 3 Unimplemented: Read as ‘0’
bit 2-0 ADCS<2:0>: Analog-to-Digital Conversion Clock Divider Select bits
(1)
111 = FADC/8
110 = FADC/7
101 = FADC/6
100 = FADC/5
011 = FADC/4 (default)
010 = FADC/3
001 = FADC/2
000 = FADC/1
REGISTER 19-1: ADCON: ADC CONTROL REGISTER (CONTINUED)
Note 1: This control bit can only be changed while the ADC is disabled (ADON = 0).