Datasheet
2011-2012 Microchip Technology Inc. DS75018C-page 231
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
19.4 ADC Control Registers
The ADC module uses the following control and status
registers:
• ADCON: ADC Control Register
• ADSTAT: ADC Status Register
• ADBASE: ADC Base Register(1)
• ADPCFG: ADC Port Configuration Register
• ADCPC0: ADC Convert Pair Control Register 0
• ADCPC1: ADC Convert Pair Control Register 1
• ADCPC3: ADC Convert Pair Control Register 3(1)
The ADCON register controls the operation of the
ADC module. The ADSTAT register displays the
status of the conversion processes. The ADPCFG
register configures the port pins as analog inputs or
as digital I/Os. The ADCPCx registers control the
triggering of the ADC conversions. See Register 19-1
through Register 19-7 for detailed bit configurations.
Note: A unique feature of the ADC module is its
ability to sample inputs in an asynchronous
manner. Individual Sample-and-Hold
circuits can be triggered independently of
each other.
REGISTER 19-1: ADCON: ADC CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0
ADON
—ADSIDLSLOWCLK
(1)
—GSWTRG—FORM
(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-1 R/W-1
EIE
(1)
ORDER
(1)
SEQSAMP
(1)
ASYNCSAMP
(1)
— ADCS<2:0>
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ADON: ADC Operating Mode bit
1 = ADC module is operating
0 = ADC module is off
bit 14 Unimplemented: Read as ‘0’
bit 13 ADSIDL: Stop in Idle Mode bit
1 = Discontinues module operation when device enters Idle mode
0 = Continues module operation in Idle mode
bit 12 SLOWCLK: Enable Slow Clock Divider bit
(1)
1 = ADC is clocked by the auxiliary PLL (ACLK)
0 = ADC is clocked by the primary PLL (FVCO)
bit 11 Unimplemented: Read as ‘0’
bit 10 GSWTRG: Global Software Trigger bit
When this bit is set by the user, it will trigger conversions if selected by the TRGSRC<4:0> bits in the
ADCPCx registers. This bit must be cleared by the user prior to initiating another global trigger (i.e., this
bit is not auto-clearing).
bit 9 Unimplemented: Read as ‘0’
Note 1: This control bit can only be changed while the ADC is disabled (ADON = 0).