Datasheet

 2011-2012 Microchip Technology Inc. DS75018C-page 227
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
FIGURE 19-2: ADC BLOCK DIAGRAM FOR THE dsPIC33FJ06GS101A DEVICE
Even Numbered Inputs with Dedicated
Shared Sample-and-Hold
Data
Format
SAR
Core
Eight
Registers
16-Bit
Sample-and-Hold (S&H) Circuits
Bus Interface
AN0
AN2
AN1
AN7
AN6
AN3