Datasheet

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302

DS75018C-page 224  2011-2012 Microchip Technology Inc.

bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bits

(2)

11 = Interrupt is set on U1RSR transfer, making the receive buffer full (i.e., has 4 data characters)

10 = Interrupt is set on U1RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters)

0x = Interrupt is set when any character is received and transferred from the U1RSR to the receive

buffer; receive buffer has one or more characters

bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)

(2)

1 = Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect

0 = Address Detect mode is disabled

bit 4 RIDLE: Receiver Idle bit (read-only)

(2)

1 = Receiver is Idle

0 = Receiver is active

bit 3 PERR: Parity Error Status bit (read-only)

(2)

1 = Parity error has been detected for the current character (character at the top of the receive FIFO)

0 = Parity error has not been detected

bit 2 FERR: Framing Error Status bit (read-only)

(2)

1 = Framing error has been detected for the current character (character at the top of the receive

FIFO)

0 = Framing error has not been detected

bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only)

(2)

1 = Receive buffer has overflowed

0 = Receive buffer has not overflowed. Clearing a previously set OERR bit (1  0 transition) will reset

the receiver buffer and the U1RSR to the empty state.

bit 0 URXDA: Receive Buffer Data Available bit (read-only)

(2)

1 = Receive buffer has data, at least one more character can be read

0 = Receive buffer is empty

Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for

information on enabling the UART module for transmit operation.

2: This bit is not available in the dsPIC33FJ06GS001 device.