Datasheet

 2011-2012 Microchip Technology Inc. DS75018C-page 223
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 18-2: U1STA: UART1 STATUS AND CONTROL REGISTER
R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0 R-1
UTXISEL1
(2)
UTXINV
(2)
UTXISEL0
(2)
— UTXBRK
(2)
UTXEN
(1,2)
UTXBF
(2)
TRMT
(2)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0
URXISEL<1:0>
(2)
ADDEN
(2)
RIDLE
(2)
PERR
(2)
FERR
(2)
OERR
(2)
URXDA
(2)
bit 7 bit 0
Legend: HC = Hardware Clearable bit C = Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15,13 UTXISEL<1:0>: Transmission Interrupt Mode Selection bits
(2)
11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result,
the transmit buffer becomes empty
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies that there is
at least one character open in the transmit buffer)
bit 14 UTXINV: Transmit Polarity Inversion bit
(2)
If IREN = 0:
1 = U1TX Idle state is ‘0’
0 = U1TX Idle state is ‘1’
If IREN =
1:
1 =IrDA
®
encoded U1TX Idle state is ‘1’
0 = IrDA encoded U1TX Idle state is ‘0’
bit 12 Unimplemented: Read as ‘0’
bit 11 UTXBRK: Transmit Break bit
(2)
1 = Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0 = Sync Break transmission is disabled or completed
bit 10 UTXEN: Transmit Enable bit
(1,2)
1 = Transmit is enabled, U1TX pin is controlled by UART1
0 = Transmit is disabled, any pending transmission is aborted and buffer is reset; U1TX pin is
controlled by port
bit 9 UTXBF: Transmit Buffer Full Status bit (read-only)
(2)
1 = Transmit buffer is full
0 = Transmit buffer is not full; at least one more character can be written
bit 8 TRMT: Transmit Shift Register Empty bit (read-only)
(2)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for
information on enabling the UART module for transmit operation.
2: This bit is not available in the dsPIC33FJ06GS001 device.