Datasheet

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
DS75018C-page 222  2011-2012 Microchip Technology Inc.
bit 4 URXINV: Receive Polarity Inversion bit
(3)
1 = U1RX Idle state is ‘0’
0 = U1RX Idle state is ‘1’
bit 3 BRGH: High Baud Rate Enable bit
(3)
1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
bit 2-1 PDSEL<1:0>: Parity and Data Selection bits
(3)
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0 STSEL: Stop Bit Selection bit
(3)
1 = Two Stop bits
0 = One Stop bit
REGISTER 18-1: U1MODE: UART1 MODE REGISTER (CONTINUED)
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for
information on enabling the UART module for receive or transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
3: This bit is not available in the dsPIC33FJ06GS001 device.