Datasheet

 2011-2012 Microchip Technology Inc. DS75018C-page 213
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
17.2 I
2
C Registers
I2C1CON and I2C1STAT are control and status
registers, respectively. The I2C1CON register is
readable and writable. The lower six bits of I2C1STAT
are read-only. The remaining bits of the I2CSTAT are
read/write:
• I2C1RSR is the shift register used for shifting data
internal to the module and the user application
has no access to it
• I2C1RCV is the receive buffer and the register to
which data bytes are written, or from which data
bytes are read
• I2C1TRN is the transmit register to which bytes
are written during a transmit operation
• The I2C1ADD register holds the slave address
• A status bit, ADD10, indicates 10-Bit Address
mode
• The I2C1BRG acts as the Baud Rate Generator
(BRG) reload value
In receive operations, I2C1RSR and I2C1RCV
together form a double-buffered receiver. When
I2C1RSR receives a complete byte, it is transferred to
I2C1RCV, and an interrupt pulse is generated.
REGISTER 17-1: I2C1CON: I2C1 CONTROL REGISTER
R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0
I2CEN
— I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC
GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN
bit 7 bit 0
Legend: HC = Hardware Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 I2CEN: I2C1 Enable bit
1 = Enables the I2C1 module and configures the SDA1 and SCL1 pins as serial port pins
0 = Disables the I2C1 module; all I
2
C pins are controlled by port functions
bit 14 Unimplemented: Read as ‘0’
bit 13 I2CSIDL: Stop in Idle Mode bit
1 = Discontinues module operation when device enters an Idle mode
0 = Continues module operation in Idle mode
bit 12 SCLREL: SCL1 Release Control bit (when operating as I
2
C slave)
1 = Releases SCL1 clock
0 = Holds SCL1 clock low (clock stretch)
If STREN =
1:
Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is clear
at beginning of slave transmission. Hardware is clear at end of slave reception.
If STREN =
0:
Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware is clear at beginning of slave
transmission.
bit 11 IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit
1 = IPMI mode is enabled; all addresses Acknowledged
0 = IPMI mode is disabled
bit 10 A10M: 10-Bit Slave Address bit
1 = I2C1ADD is a 10-bit slave address
0 = I2C1ADD is a 7-bit slave address
bit 9 DISSLW: Disable Slew Rate Control bit
1 = Slew rate control is disabled
0 = Slew rate control is enabled