Datasheet

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
DS75018C-page 194  2011-2012 Microchip Technology Inc.
REGISTER 15-10: SPHASEx: PWMx SECONDARY PHASE SHIFT REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SPHASEx<15:8>
(1,2)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SPHASEx<7:0>
(1,2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 SPHASEx<15:0>: Secondary Phase Offset for PWMxL Output Pin bits
(1,2)
(used in Independent PWM mode only)
Note 1: If the ITB (PWMCONx<9>) bit = 0, the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00, 01
or 10), SPHASEx<15:0> = Not used.
• True Independent Output mode PMOD<1:0> (IOCONx<11:10>) = 11),
PHASEx<15:0> = Phase shift value for PWMxL only.
2: If the ITB (PWMCONx<9>) bit = 1, the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (PMOD<1:0> (IOCONx<11:10>) = 00, 01
or 10), SPHASEx<15:0> = Not used.
• True Independent Output mode PMOD<1:0> (IOCONx<11:10>) = 11),
PHASEx<15:0> = Independent time base period value for PWMxL only.