Datasheet

 2011-2012 Microchip Technology Inc. DS75018C-page 191
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
bit 2 CAM: Center-Aligned Mode Enable bit
(2,3)
1 = Center-Aligned mode is enabled
0 = Center-Aligned mode is disabled
bit 1 XPRES: External PWM Reset Control bit
(4)
1 = Current-limit source resets time base for this PWM generator if it is in Independent Time Base mode
0 = External pins do not affect PWM time base
bit 0 IUE: Immediate Update Enable bit
1 = Updates to the active MDC/PDCx/SDCx registers are immediate
0 = Updates to the active MDC/PDCx/SDCx registers are synchronized to the PWM time base
REGISTER 15-6: PWMCONx: PWMx CONTROL REGISTER (CONTINUED)
Note 1: Software must clear the interrupt status here and the corresponding IFSx bit in the interrupt controller.
2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
3: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
4: To operate in External Period Reset mode, configure the CLMOD (FCLCONx<8>) bit = 0 and
ITB (PWMCONx<9>) bit = 1.