Datasheet

 2011-2012 Microchip Technology Inc. DS75018C-page 189
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 15-4: SEVTCMP: PWM SPECIAL EVENT COMPARE REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SEVTCMP <15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
SEVTCMP <7:3>
— — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 SEVTCMP<15:3>: Special Event Compare Count Value bits
bit 2-0 Unimplemented: Read as ‘0’
REGISTER 15-5: MDC: PWM MASTER DUTY CYCLE REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MDC<15:8>
(1,2)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
MDC<7:0>
(1,2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 MDC<15:0>: Master PWM Duty Cycle Value bits
(1,2)
Note 1: The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0009,
while the maximum pulse width generated corresponds to a value of Period – 0x0008.
2: As the duty cycle gets closer to 0% or 100% of the PWM period (0 ns-40 ns, depending on the mode of
operation), the PWM duty cycle resolution will degrade from 1 LSb to 3 LSbs.