Datasheet

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
DS75018C-page 186  2011-2012 Microchip Technology Inc.
FIGURE 15-2: PARTITIONED OUTPUT PAIR, COMPLEMENTARY PWM MODE
15.3 PWM Control Registers
The following registers control the operation of the
high-speed PWM module.
• PTCON: PWM Time Base Control Register
• PTCON2: PWM Clock Divider Select Register 2
• PTPER: PWM Master Time Base Register(1)
• SEVTCMP: PWM Special Event Compare
Register
• MDC: PWM Master Duty Cycle Register
• PWMCONx: PWMx Control Register
• PDCx: PWMx Generator Duty Cycle Register(1)
• PHASEx: PWMx Primary Phase Shift Register
• DTRx: PWMx Dead-Time Register
• ALTDTRx: PWMx Alternate Dead-Time Register
• SDCx: PWMx Secondary Duty Cycle Register(1)
• SPHASEx: PWMx Secondary Phase Shift
Register
• TRGCONx: PWMx Trigger Control Register
• IOCONx: PWMx I/O Control Register
• FCLCONx: PWMx Fault Current-Limit Control
Register
• TRIGx: PWMx Primary Trigger Compare Value
Register
• STRIGx: PWMx Secondary Trigger Compare
Value Register
• LEBCONx: PWMx Leading-Edge Blanking
Control Register
• PWMCAPx: Primary PWMx Time Base Capture
Register
• CHOP: PWM Chop Clock Generator Register
• AUXCONx: PWMx Auxiliary Control Register
PWM Duty Cycle Register
Duty Cycle Comparator
Channel Override Values
Fault Pin Assignment Logic
Fault Pin
PWMXH
PWMXL
TMRx < PDC
PWM
Override
Logic
Dead-Time
Logic
Fault Active
Phase Offset
M
U
X
M
U
X
Timer/Counter
Fault Override Values