Datasheet

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
DS75018C-page 180  2011-2012 Microchip Technology Inc.
14.1 Output Compare Modes
Configure the Output Compare modes by setting the
appropriate Output Compare Mode (OCM<2:0>) bits in
the Output Compare Control (OC1CON<2:0>) register.
Table 14-1 lists the different bit settings for the Output
Compare modes. Figure 14-2 illustrates the output
compare operation for various modes. The user
application must disable the associated timer when
writing to the Output Compare Control registers to
avoid malfunctions.
TABLE 14-1: OUTPUT COMPARE MODES
FIGURE 14-2: OUTPUT COMPARE OPERATION
Note: Refer to Section 13. “Output Compare”
(DS70209) in the “dsPIC33F/PIC24H
Family Reference Manual” for OC1R and
OC1RS register restrictions.
OCM<2:0> Mode OC1 Pin Initial State OC1 Interrupt Generation
000 Module Disabled Controlled by GPIO register —
001 Active-Low One-Shot 0 OC1 rising edge
010 Active-High One-Shot 1 OC1 falling edge
011 Toggle Current output is maintained OC1 rising and falling edge
100 Delayed One-Shot 0 OC1 falling edge
101 Continuous Pulse 0 OC1 falling edge
110 PWM without Fault Protection ‘0’ if OC1R is zero,
‘1’ if OC1R is non-zero
No interrupt
111 PWM with Fault Protection ‘0’ if OC1R is zero,
‘1’ if OC1R is non-zero
OCFA
falling edge for OC1 to OC4
OC1RS
TMRx
OC1R
Timerx is Reset on
Period Match
Continuous Pulse
(OCM<2:0> = 101)
PWM
(OCM<2:0> = 110 or 111)
Active-Low One-Shot
(OCM<2:0> = 001)
Active-High One-Shot
(OCM<2:0> = 010)
Toggle
(OCM<2:0> = 011)
Delayed One-Shot
(OCM<2:0> = 100)
Output Compare
Mode Enabled