Datasheet

 2011-2012 Microchip Technology Inc. DS75018C-page 173
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
11.0 TIMER1
The Timer1 module is a 16-bit timer, which can serve
as a time counter for the Real-Time Clock (RTC) or
operate as a free-running interval timer/counter.
The Timer1 module has the following unique features
over other timers:
• Can be operated from the low-power 32 kHz
crystal oscillator available on the device
• Can be operated in Asynchronous Counter mode
from an external clock source
• The Timer1 External Clock Input (T1CK) can
optionally be synchronized to the internal device
clock and the clock synchronization is performed
after the prescaler
The unique features of Timer1 allow it to be used for
Real-Time Clock applications. A block diagram of
Timer1 is shown in Figure 11-1.
The Timer1 module can operate in one of the following
modes:
• Timer mode
• Gated Timer mode
• Synchronous Counter mode
• Asynchronous Counter mode
In Timer and Gated Timer modes, the input clock is
derived from the internal instruction cycle clock (F
CY).
In Synchronous and Asynchronous Counter modes,
the input clock is derived from the external clock input
at the T1CK pin.
The Timer1 modes are determined by the following bits:
• Timer1 Clock Source Control bit: TCS (T1CON<1>)
• Timer1 Synchronization Control bit: TSYNC
(T1CON<2>)
• Timer1 Gate Control bit: TGATE (T1CON<6>)
The Timer1 control bit settings for different operating
modes are given in the Table 11-1.
TABLE 11-1: TIMER1 MODE SETTINGS
FIGURE 11-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS001/101A/102A/
202A and dsPIC33FJ09GS302 families
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 11. “Timers”
(DS70205) in the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Mode TCS TGATE TSYNC
Timer1 00x
Gated Timer1 01x
Synchronous
Counter
1x1
Asynchronous
Counter
1x0
TGATE
TCS
00
10
x1
Comparator
PR1
TGATE
Set T1IF Flag
0
1
TSYNC
1
0
Sync
Equal
Reset
T1CK
Prescaler
(/n)
TCKPS<1:0>
FP
Falling Edge
Detect
Prescaler
(/n)
TCKPS<1:0>
Gate
Sync
TMR1