Datasheet

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
DS75018C-page 16  2011-2012 Microchip Technology Inc.
CMP1A
CMP1B
CMP1C
CMP1D
CMP2A
CMP2B
CMP2C
CMP2D
I
I
I
I
I
I
I
I
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
No
No
No
No
No
No
No
No
Comparator 1 Channel A.
Comparator 1 Channel B.
Comparator 1 Channel C.
Comparator 1 Channel D.
Comparator 2 Channel A.
Comparator 2 Channel B.
Comparator 2 Channel C.
Comparator 2 Channel D.
DACOUT O — No DAC output voltage.
ACMP1-ACMP2 O — Yes DAC trigger to PWM module.
ISRC1
(2)
ISRC2
(2)
ISRC3
(2)
ISRC4
(2)
O
O
O
O
—
—
—
—
No
No
No
No
Constant Current Source Output 1.
Constant Current Source Output 2.
Constant Current Source Output 3.
Constant Current Source Output 4.
EXTREF I Analog No External voltage reference input for the reference DACs.
REFCLKO O — Yes REFCLKO output signal is a postscaled derivative of the system
clock.
FLT1-FLT8 I ST Yes Fault inputs to PWM module.
SYNCI1-SYNCI2
SYNCO1
PWM1L
PWM1H
PWM2L
PWM2H
PWM4L
PWM4H
I
O
O
O
O
O
O
O
ST
—
—
—
—
—
—
—
Yes
Yes
No
No
No
No
Yes
Yes
External synchronization signal to PWM master time base.
PWM master time base for external device synchronization.
PWM1 low output.
PWM1 high output.
PWM2 low output.
PWM2 high output.
PWM4 low output.
PWM4 high output.
PGED1
PGEC1
PGED2
PGEC2
PGED3
(1)
PGEC3
(1)
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
No
No
No
No
No
No
Data I/O pin for programming/debugging Communication Channel 1.
Clock input pin for programming/debugging Communication
Channel 1.
Data I/O pin for programming/debugging Communication Channel 2.
Clock input pin for programming/debugging Communication
Channel 2.
Data I/O pin for programming/debugging Communication Channel 3.
Clock input pin for programming/debugging Communication
Channel 3.
MCLR
I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the
device.
AVDD P P No Positive supply for analog modules. This pin must be connected
at all times. AVDD is connected to VDD on 18 and 28-pin devices.
AVSS P P No Ground reference for analog modules. AV
SS is connected to VSS
on 18 and 28-pin devices.
V
DD P — No Positive supply for peripheral logic and I/O pins.
V
CAP P — No CPU logic filter capacitor connection.
V
SS P — No Ground reference for logic and I/O pins.
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Type
Buffer
Type
PPS
Capable
Description
Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input
ST = Schmitt Trigger input with CMOS levels P = Power O = Output
TTL = Transistor-Transistor Logic PPS = Peripheral Pin Select — = Does not apply
Note 1: Not all pins are available on all devices. Refer to the specific device in the “Pin Diagrams” section for
availability.
2: This pin is available on dsPIC33FJ09GS302 devices only.