Datasheet

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
DS75018C-page 148  2011-2012 Microchip Technology Inc.
10.6 Peripheral Pin Select (PPS)
Peripheral Pin Select configuration enables peripheral
set selection and placement on a wide range of I/O
pins. By increasing the pinout options available on a
particular device, programmers can better tailor the
microcontroller to their entire application, rather than
trimming the application to fit the device.
The Peripheral Pin Select configuration feature operates
over a fixed subset of digital I/O pins. Programmers can
independently map the input and/or output of most
digital peripherals to any one of these I/O pins.
Peripheral Pin Select is performed in software and gen-
erally does not require the device to be reprogrammed.
Hardware safeguards are included that prevent acciden-
tal or spurious changes to the peripheral mapping once
it has been established.
10.6.1 AVAILABLE PINS
The Peripheral Pin Select feature is used with a range
of up to 16 pins. The number of available pins depends
on the particular device and its pin count. Pins that
support the Peripheral Pin Select feature include the
designation, “RPn”, in their full pin designation, where
“RP” designates a remappable peripheral and “n” is the
remappable pin number.
10.6.2 CONTROLLING PERIPHERAL PIN
SELECT
Peripheral Pin Select features are controlled through
two sets of Special Function Registers: one to map
peripheral inputs and one to map outputs. Because
they are separately controlled, a particular peripheral’s
input and output (if the peripheral has both) can be
placed on any selectable function pin without
constraint.
The association of a peripheral to a peripheral select-
able pin is handled in two different ways, depending on
whether an input or output is being mapped.
10.6.2.1 Input Mapping
The inputs of the Peripheral Pin Select options are
mapped on the basis of the peripheral. A control register
associated with a peripheral dictates the pin it will be
mapped to. The RPINRx registers are used to configure
peripheral input mapping (see Register 10-1 through
Register 10-15). Each register contains sets of 6-bit
fields, with each set associated with one of the
remappable peripherals. Programming a given
peripheral’s bit field with an appropriate 6-bit value maps
the RPn pin with that value to that peripheral. For any
given device, the valid range of values for any bit field
corresponds to the maximum number of Peripheral Pin
Selections supported by the device.
Figure 10-2 illustrates the remappable pin selection for
the U1RX input.
FIGURE 10-2: REMAPPABLE MUX
INPUT FOR U1RX
Note: For input mapping only, the Peripheral Pin
Select (PPS) functionality does not have
priority over the TRISx settings. There-
fore, when configuring the RPx pin for
input, the corresponding bit in the TRISx
register must also be configured for input
(i.e., set to ‘1’).
RP0
RP1
RP2
RP15
0
15
1
2
U1RX Input
U1RXR<5:0>
to Peripheral