Datasheet

 2011-2012 Microchip Technology Inc. DS75018C-page 143
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 9-6: PMD7: PERIPHERAL MODULE DISABLE CONTROL REGISTER 7
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — —CMP2MD
(1)
CMP1MD
(1)
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-10 Unimplemented: Read as ‘0’
bit 9 CMP2MD: Analog Comparator 2 Module Disable bit
(1)
1 = Analog Comparator 2 module is disabled
0 = Analog Comparator 2 module is enabled
bit 8 CMP1MD: Analog Comparator 1 Module Disable bit
(1)
1 = Analog Comparator 1 module is disabled
0 = Analog Comparator 1 module is enabled
bit 7-0 Unimplemented: Read as ‘0’
Note 1: This bit is not implemented in dsPIC33FJ06GS101A/102A devices.