Datasheet

 2011-2012 Microchip Technology Inc. DS75018C-page 141
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 9-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3
REGISTER 9-4: PMD4: PERIPHERAL MODULE DISABLE CONTROL REGISTER 4
U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0
— — — — —CMPMD
(1)
— —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10 CMPMD: Analog Comparator Module Disable bit
(1)
1 = Analog comparator module is disabled
0 = Analog comparator module is enabled
bit 9-0 Unimplemented: Read as ‘0’
Note 1: This bit is not implemented in dsPIC33FJ06GS101A/102A devices.
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0
— — — —REFOMD— — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-4 Unimplemented: Read as ‘0’
bit 3 REFOMD: Reference Clock Generator Module Disable bit
1 = Reference clock generator module is disabled
0 = Reference clock generator module is enabled
bit 2-0 Unimplemented: Read as ‘0’