Datasheet

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
DS75018C-page 140  2011-2012 Microchip Technology Inc.
REGISTER 9-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — —IC1MD
(1)
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — —OC1MD
(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-9 Unimplemented: Read as ‘0’
bit 8 IC1MD: Input Capture 1 Module Disable bit
(1)
1 = Input Capture 1 module is disabled
0 = Input Capture 1 module is enabled
bit 7-1 Unimplemented: Read as ‘0’
bit 0 OC1MD: Output Compare 1 Module Disable bit
(2)
1 = Output Compare 1 module is disabled
0 = Output Compare 1 module is enabled
Note 1: This bit is not implemented in dsPIC33FJ06GS001/101A/102A devices.
2: This bit is not implemented in the dsPIC33FJ06GS001 device.