Datasheet

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
DS75018C-page 14  2011-2012 Microchip Technology Inc.
FIGURE 1-1: dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 BLOCK DIAGRAM
16
OSC1/CLKI
OSC2/CLKO
V
DD, VSS
Timing
Generation
MCLR
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
FRC/LPRC
Oscillators
Regulator
Voltage
VCAP
IC1
I2C1
PORTA
Instruction
Decode and
Control
PCH PCL
16
Program Counter
16-Bit ALU
23
23
24
23
Instruction Reg
PCU
16 x 16
W Register Array
ROM Latch
16
EA MUX
16
16
8
Interrupt
Controller
PSV and Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Data Latch
Address
Latch
Address Latch
Program
Data Latch
Literal Data
16
16
16
16
Data Latch
Address
Latch
16
X RAM
Y RAM
16
Y Data Bus
X Data Bus
DSP Engine
Divide Support
16
Control Signals
to Various Blocks
ADC1Timer1,2
PORTB
Address Generator Units
CNx
UART1
PWM
3 x 2
Remappable
Pins
SPI1
OC1
Analog
Comparator 1, 2
Note: Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features
present on each device.
Reference
Constant
Current
Source
Clock
Memory