Datasheet

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
DS75018C-page 134  2011-2012 Microchip Technology Inc.
8.5 Clock Switching Operation
Applications are free to switch among any of the four
clock sources (primary, LP, FRC and LPRC) under
software control at any time. To limit the possible side
effects of this flexibility, devices have a safeguard lock
built into the switch process.
8.5.1 ENABLING CLOCK SWITCHING
To enable clock switching, the FCKSM1 Configuration bit
in the FOSC Configuration register must be programmed
to ‘0’. (Refer to Section 22.1 “Configuration Bits” for
further details.) If the FCKSM1 Configuration bit is unpro-
grammed (‘1’), the clock switching function and Fail-Safe
Clock Monitor function are disabled. This is the default
setting.
The NOSC<2:0> control bits (OSCCON<10:8>) do not
control the clock selection when clock switching
is disabled. However, the COSC<2:0> bits
(OSCCON<14:12>) reflect the clock source selected
by the FNOSC Configuration bits.
The OSWEN control bit (OSCCON<0>) has no effect
when clock switching is disabled. It is held at ‘0’ at all
times.
8.5.2 OSCILLATOR SWITCHING SEQUENCE
To perform a clock switch, the following basic sequence
is required:
1. If desired, read the COSC<2:0> bits to
determine the current oscillator source.
2. Perform the unlock sequence to allow a write to
the OSCCON register high byte.
3. Write the appropriate value to the NOSC<2:0>
control bits for the new oscillator source.
4. Perform the unlock sequence to allow a write to
the OSCCON register low byte.
5. Set the OSWEN bit (OSCCON<0>) to initiate the
oscillator switch.
Once the basic sequence is completed, the system
clock hardware responds automatically as follows:
1. The clock switching hardware compares the
COSC<2:0> status bits with the new value of the
NOSC<2:0> control bits. If they are the same,
the clock switch is a redundant operation. In this
case, the OSWEN bit is cleared automatically
and the clock switch is aborted.
2. If a valid clock switch has been initiated, the
LOCK (OSCCON<5>) and the CF
(OSCCON<3>) status bits are cleared.
3. The new oscillator is turned on by the hardware
if it is not currently running. If a crystal oscillator
must be turned on, the hardware waits until the
Oscillator Start-up Timer (OST) expires. If the
new source is using the PLL, the hardware waits
until a PLL lock is detected (LOCK = 1).
4. The hardware waits for 10 clock cycles from the
new clock source and then performs the clock
switch.
5. The hardware clears the OSWEN bit to indicate a
successful clock transition. In addition, the
NOSC<2:0> bit values are transferred to the
COSC<2:0> status bits.
6. The old clock source is turned off at this time,
with the exception of LPRC (if WDT or FSCM is
enabled).
Note: Primary Oscillator mode has three different
submodes (XT, HS and EC), which are
determined by the POSCMD<1:0>
Configuration bits. While an application
can switch to and from Primary Oscillator
mode in software, it cannot switch among
the different primary submodes without
reprogramming the device.
Note 1: The processor continues to execute code
throughout the clock switching sequence.
Timing-sensitive code should not be
executed during this time.
2: Direct clock switches between any
Primary Oscillator mode with PLL and
FRCPLL mode are not permitted. This
applies to clock switches in either direc-
tion. In these instances, the application
must switch to FRC mode as a transition
clock source between the two PLL modes.
3: Refer to Section 42. “Oscillator
(Part IV)” (DS70307) in the “dsPIC33F/
PIC24H Family Reference Manual” for
details.