Datasheet

 2011-2012 Microchip Technology Inc. DS75018C-page 127
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
bit 4 Unimplemented: Read as ‘0’
bit 3 CF: Clock Fail Detect bit (read/clear by application)
1 = FSCM has detected clock failure
0 = FSCM has not detected clock failure
bit 2-1 Unimplemented: Read as ‘0’
bit 0 OSWEN: Oscillator Switch Enable bit
1 = Request oscillator switch to selection specified by NOSC<2:0> bits
0 = Oscillator switch is complete
REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER
(1,3)
(CONTINUED)
Note 1: Writes to this register require an unlock sequence. Refer to Section 42. “Oscillator (Part IV)” (DS70307)
in the “dsPIC33F/PIC24H Family Reference Manual” for details.
2: Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not permit-
ted. This applies to clock switches in either direction. In these instances, the application must switch to
FRC mode as a transition clock source between the two PLL modes.
3: This register is reset only on a Power-on Reset (POR).