Datasheet

 2011-2012 Microchip Technology Inc. DS75018C-page 123
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
8.0 OSCILLATOR CONFIGURATION
The oscillator system provides:
• External and internal oscillator options as clock
sources
• An on-chip Phase Lock Loop (PLL) to scale the
internal operating frequency to the required system
clock frequency
• An internal FRC oscillator that can also be used with
the PLL, thereby allowing full-speed operation
without any external clock generation hardware
• Clock switching between various clock sources
• Programmable clock postscaler for system power
savings
• A Fail-Safe Clock Monitor (FSCM) that detects clock
failure and takes fail-safe measures
• An Oscillator Control register (OSCCON)
• Nonvolatile Configuration bits for main oscillator
selection
• An auxiliary PLL for ADC and PWM
A simplified diagram of the oscillator system is shown
in Figure 8-1.
FIGURE 8-1: OSCILLATOR SYSTEM DIAGRAM
Note 1: This data sheet summarizes the features
of the dsPIC33FJ06GS001/101A/102A/
202A and dsPIC33FJ09GS302 families
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 42. “Oscillator
(Part IV)” (DS70307) in the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
XTPLL, HSPLL,
XT, HS, EC
FRCDIV<2:0>
WDT, PWRT,
FSCM
FRCDIVN
FRCDIV16
ECPLL, FRCPLL
NOSC<2:0> FNOSC<2:0>
Reset
LPRC
Oscillator
DOZE<2:0>
S3
S1
S2
S1/S3
S7
S6
FRC
LPRC
S0
S5
÷ 16
Clock Switch
S7
Clock Fail
÷
2
TUN<5:0>
PLL
(1)
FCY
(3)
FOSC
FRCDIV
DOZE
ACLK, FADC
SELACLK APSTSCLR<2:0>
To PWM/ADC
(1)
ENAPLL
POSCMD<1:0>
F
VCO
(1)
APLL
(1)
x16
ASRCSEL FRCSEL
POSCCLK
FRCCLK
FRCCLK
POSCCLK
ROSEL RODIV<3:0>
REFCLKO
POSCCLK
Reference Clock Generation
Auxiliary Clock Generation
RPx
Note 1: See Section 8.1.3 “PLL Configuration” and Section 8.2 “Auxiliary Clock Generation” for configuration restrictions.
2: If the oscillator is used with XT or HS modes, an external parallel resistor with the value of 1 M must be connected.
3: The term, F
P, refers to the clock source for all the peripherals, while FCY refers to the clock source for the CPU. Throughout this
document, F
P and FCY are used interchangeably, except in the case of Doze mode. FP and FCY will be different when Doze mode is
used in any ratio other than 1:1, which is the default.
F
VCO
(1)
FOSC
FP
(3)
OSC2
OSC1
Primary Oscillator
R
(2)
To L FSR
FRC
Oscillator
÷ N
÷ N