Datasheet

 2011-2012 Microchip Technology Inc. DS75018C-page 119
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-33: IPC28: INTERRUPT PRIORITY CONTROL REGISTER 28
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
— ADCP3IP<2:0>
(1)
— ADCP2IP<2:0>
(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-7 Unimplemented: Read as ‘0’
bit 6-4 ADCP3IP<2:0>: ADC Pair 3 Conversion Done Interrupt Priority bits
(1)
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3 Unimplemented: Read as ‘0’
bit 2-0 ADCP2IP<2:0>: ADC Pair 2 Conversion Done Interrupt Priority bits
(2)
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
Note 1: These bits are not implemented in dsPIC33FJ06GS102A/202A devices.
2: These bits are not implemented in dsPIC33FJ06GS001/101A devices.