Datasheet

 2011-2012 Microchip Technology Inc. DS75018C-page 115
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-29: IPC23: INTERRUPT PRIORITY CONTROL REGISTER 23
U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0
—PWM2IP
(1)
— PWM1IP<2:0>
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 Unimplemented: Read as ‘0’
bit 14-12 PWM2IP<2:0>: PWM2 Interrupt Priority bits
(1)
111 = Interrupt is Priority 7 (highest priority)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 11 Unimplemented: Read as ‘0’
bit 10-8 PWM1IP<2:0>: PWM1 Interrupt Priority bits
111 = Interrupt is Priority 7 (highest priority)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7-0 Unimplemented: Read as ‘0’
Note 1: These bits are not implemented in dsPIC33FJ06GS001/101A devices.