Datasheet

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
DS75018C-page 106  2011-2012 Microchip Technology Inc.
REGISTER 7-18: IEC7: INTERRUPT ENABLE CONTROL REGISTER 7
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0
— — — ADCP6IE — — ADCP3IE
(1)
ADCP2IE
(2)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-5 Unimplemented: Read as ‘0’
bit 4 ADCP6IE: ADC Pair 6 Conversion Done Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 3-2 Unimplemented: Read as ‘0’
bit 1 ADCP3IE: ADC Pair 3 Conversion Done Interrupt Enable bit
(1)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0 ADCP2IE: ADC Pair 2 Conversion Done Interrupt Enable bit
(2)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
Note 1: This bit is not implemented in dsPIC33FJ06GS102A/202A devices.
2: This bit is not implemented in dsPIC33FJ06GS001/101A devices.