Datasheet

 2011-2012 Microchip Technology Inc. DS75018C-page 105
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-17: IEC6: INTERRUPT ENABLE CONTROL REGISTER 6
R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0
ADCP1IE ADCP0IE — — — — — —
bit 15 bit 8
R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0
AC2IE
(1)
— — — — —PWM4IE
(2)
—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ADCP1IE: ADC Pair 1 Conversion Done Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 14 ADCP0IE: ADC Pair 0 Conversion Done Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 13-8 Unimplemented: Read as ‘0
bit 7 AC2IE: Analog Comparator 2 Interrupt Enable bit
(1)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 6-2 Unimplemented: Read as ‘0’
bit 1 PWM4IE: PWM4 Interrupt Enable bit
(2)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0 Unimplemented: Read as ‘0’
Note 1: This bit is not implemented in dsPIC33FJ06GS101A/102A devices.
2: This bit is not implemented in dsPIC33FJ06GS102A/202A devices.