Datasheet

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
DS75018C-page 104  2011-2012 Microchip Technology Inc.
REGISTER 7-16: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5
R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0
PWM2IE
(1)
PWM1IE — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — —JTAGIE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 PWM2IE: PWM2 Interrupt Enable bit
(1)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 14 PWM1IE: PWM1 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 13-1 Unimplemented: Read as ‘0’
bit 0 JTAGIE: JTAG Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
Note 1: This bit is not implemented in dsPIC33FJ06GS001/101A devices.