Datasheet

 2011-2012 Microchip Technology Inc. DS75018C-page 103
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-14: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3
REGISTER 7-15: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0
— — — — — — PSEMIE —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-10 Unimplemented: Read as ‘0’
bit 9 PSEMIE: PWM Special Event Match Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 8-0 Unimplemented: Read as ‘0’
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0
— — — — — —U1EIE
(1)
—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-2 Unimplemented: Read as ‘0’
bit 1 U1EIE: UART1 Error Interrupt Enable bit
(1)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0 Unimplemented: Read as ‘0’
Note 1: This bit is not implemented in the dsPIC33FJ06GS001 device.