Datasheet

dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
DS75018C-page 102  2011-2012 Microchip Technology Inc.
REGISTER 7-13: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1
U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
— —INT2IE— — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — INT1IE CNIE AC1IE
(1)
MI2C1IE SI2C1IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 INT2IE: External Interrupt 2 Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 12-5 Unimplemented: Read as ‘0’
bit 4 INT1IE: External Interrupt 1 Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 3 CNIE: Input Change Notification Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 2 AC1IE: Analog Comparator 1 Interrupt Enable bit
(1)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 1 MI2C1IE: I2C1 Master Events Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0 SI2C1IE: I2C1 Slave Events Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
Note 1: This bit is not implemented in dsPIC33FJ06GS101A/102A devices.