Datasheet

 2011-2012 Microchip Technology Inc. DS75018C-page 101
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302
REGISTER 7-12: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
— —ADIEU1TXIE
(1)
U1RXIE
(1)
SPI1IE
(1)
SPI1EIE
(1)
—
bit 15 bit 8
R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
T2IE
— — —T1IEOC1IE
(1)
IC1IE
(2)
INT0IE
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 Unimplemented: Read as ‘0’
bit 13 ADIE: ADC1 Conversion Complete Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 12 U1TXIE: UART1 Transmitter Interrupt Enable bit
(1)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 11 U1RXIE: UART1 Receiver Interrupt Enable bit
(1)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 10 SPI1IE: SPI1 Event Interrupt Enable bit
(1)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 9 SPI1EIE: SPI1 Event Interrupt Enable bit
(1)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 8 Unimplemented: Read as ‘0’
bit 7 T2IE: Timer2 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 6-4 Unimplemented: Read as ‘0’
bit 3 T1IE: Timer1 Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit
(1)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit
(2)
1 = Interrupt request is enabled
0 = Interrupt request not enabled
bit 0 INT0IE: External Interrupt 0 Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
Note 1: This bit is not implemented in dsPIC33FJ06GS001/101A/102A devices.
2: This bit is not implemented in the dsPIC33FJ06GS001 device.