Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller VTLA 36 (5x5) 16-Bit 40 null I/O number 21

 2011-2012 Microchip Technology Inc. DS75018C-page 1

dsPIC33FJ06GS001/101A/102A/202A

and dsPIC33FJ09GS302

Operating Conditions

• 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS

Core: 16-Bit dsPIC33F CPU

• Code Efficient (C and Assembly) Architecture

• Two 40-Bit Wide Accumulators

• Single-Cycle (MAC/MPY) with Dual Data Fetch

• Single-Cycle Mixed-Sign MUL plus Hardware Divide

• 32-Bit Multiply Support

Clock Management

• ±2% Internal Oscillator

• Programmable PLLs and Oscillator Clock Sources

• Fail-Safe Clock Monitor (FSCM)

• Independent Watchdog Timer (WDT)

• Fast Wake-up and Start-up

Power Management

• Low-Power Management modes (Sleep, Idle, Doze)

• Integrated Power-on Reset and Brown-out Reset

• 2.0 mA/MHz Dynamic Current (typical)

•135 µA I

PD Current (typical)

High-Speed PWM

• Up to Three PWM Pairs with Independent Timing

• Dead Time for Rising and Falling Edges

• 1.04 ns PWM Resolution for Dead Time, Duty Cycle,

Phase and Frequency

• PWM Support for:

- DC/DC, AC/DC, Inverters, PFC and Lighting

• Programmable Fault Inputs

• Flexible Trigger Configurations for ADC Conversions

Advanced Analog Features

• Two High-Speed Comparators with Direct Connection to

the PWM module:

- Buffered/amplified output drive

- Independent 10-bit DAC for each comparator

- Rail-to-rail comparator operation

- DACOUT amplifier (1x, 1.8x)

- Selectable hysteresis

- Programmable output polarity

- Interrupt generation capability

Advanced Analog Features (Continued)

• ADC module:

- 10-bit resolution with Successive Approximation

Sample-and-Hold (S&H) circuits

- Up to 8 input channels grouped into four conversion

pairs, plus two inputs for monitoring voltage references

- Flexible and independent ADC trigger sources

- Dedicated Result register for each

analog channel

Timers/Output Compare/Input Capture

• Two 16-Bit General Purpose Timers/Counters

• Input Capture module

• Output Compare module

• Peripheral Pin Select (PPS) to allow Function Remap

Communication Interfaces

• UART module (10 Mbps):

- With support for LIN/J2602 protocols and IrDA

• 4-Wire SPI module

•I

C™ module (up to 1 Mbaud) with SMBus Support

• PPS to allow Function Remap

Input/Output

• Constant Current Source:

- Constant current generator (10 µA nominal)

• Sink/Source 18 mA on 8 Pins and 6 mA on 13 Pins

• 5V Tolerant Pins

• Selectable Open-Drain and Pull-ups

• External Interrupts on 16 I/O Pins

Qualification and Class B Support

• AEC-Q100 REVG (Grade 1, -40ºC to +125ºC) Planned

• Class B Safety Library, IEC 60730

Debugger Development Support

• In-Circuit and In-Application Programming

• Two Breakpoints

• IEEE 1149.2 Compatible (JTAG) Boundary Scan

• Trace and Run-Time Watch

16-Bit Microcontrollers and Digital Signal Controllers with

High-Speed PWM, ADC and Comparators

Summary of content (352 pages)

PAGE 1
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 16-Bit Microcontrollers and Digital Signal Controllers with High-Speed PWM, ADC and Comparators Operating Conditions Advanced Analog Features (Continued) • 3.0V to 3.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 PRODUCT FAMILIES The device names, pin counts, memory sizes and peripheral availability of each device are listed in Table 1. The following pages show their pinout diagrams.
PAGE 3
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Pin Diagrams = Pins are up to 5V tolerant 18-Pin SOIC, PDIP 1 18 2 17 VSS AN1/CMP1B/RA1 3 16 PWM1L/RA3 15 PWM1H/RA4 14 VCAP 13 VSS 12 11 PGEC1/SDA1/RP7(1)/CN7/RB7 PGED1/TDI/SCL1/RP6(1)/CN6/RB6 TDO/RP5(1)/CN5/RB5 dsPIC33FJ06GS001 MCLR AN0/CMP1A/RA0 AN2/CMP1C/CMP2A/RA2 4 AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0 5 OSC1/CLKI/AN6/RP1(1)/CN1/RB1 6 OSC2/CLKO/AN7/RP2(1)/CN2/RB2 PGED2/TCK/INT0/RP3(1)/CN3/RB3 7 8 PGEC2/TMS/EXTREF/RP4(1)/CN4/RB4 9
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Pin Diagrams (Continued) = Pins are up to 5V tolerant 28-Pin SOIC, SPDIP, SSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 dsPIC33FJ06GS102A MCLR AN0/RA0 AN1/RA1 AN2/RA2 (1) AN3/RP0 /CN0/RB0 AN4/RP9(1)/CN9/RB9 AN5/RP10(1)/CN10/RB10 VSS OSC1/CLKI/RP1(1)/CN1/RB1 (1) OSC2/CLKO/RP2 /CN2/RB2 PGED2/INT0/RP3(1)/CN3/RB3 PGEC2/RP4(1)/CN4/RB4 VDD PGED3/RP8(1)/CN8/RB8 28 27 26 25 24 23 22 21 20 19 18 17 16 15 = Pins are up to 5V tolerant 28-Pin SPDIP, SOIC, SSOP 1 2 3
PAGE 5
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Pin Diagrams (Continued) = Pins are up to 5V tolerant AN1/RA1 AN0/RA0 MCLR AVDD AVSS PWM1L/RA3 PWM1H/RA4 28-Pin QFN-S(2) 28 27 26 25 24 23 22 AN2/RA2 AN3/RP0(1)/CN0/RB0 AN4/RP9(1)/CN9/RB9 AN5/RP10(1)/CN10/RB10 VSS OSC1/CLKI/RP1(1)/CN1/RB1 OSC2/CLKO/RP2(1)/CN2/RB2 PWM2L/RP14(1)/CN14/RB14 PWM2H/RP13(1)/CN13/RB13 TCK/RP12(1)/CN12/RB12 TMS/RP11(1)/CN11/RB11 VCAP VSS PGEC1/SDA1/RP7(1)/CN7/RB7 PWM1L/RA3 PWM1H/RA4 AVDD AVSS = Pins are up to 5V tolerant M
PAGE 6
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Pin Diagrams (Continued) 28-Pin QFN-S(2) AN1/CMP1B/RA1 AN0/CMP1A/RA0 MCLR AVDD AVSS PWM1L/RA3 PWM1H/RA4 = Pins are up to 5V tolerant 28 27 26 25 24 23 22 1 2 3 4 dsPIC33FJ09GS302 5 6 7 8 9 10 11 12 13 14 21 20 19 18 17 16 15 PWM2L/RP14(1)/CN14/RB14 PWM2H/RP13(1)/CN13/RB13 TCK/RP12(1)/CN12/RB12 TMS/RP11(1)/CN11/RB11 VCAP VSS PGEC1/SDA1/RP7(1)/CN7/RB7 PGED2/DACOUT/INT0/RP3(1)/CN3/RB3 PGEC2/EXTREF/RP4(1)/CN4/RB4 VDD PGED3/RP8(1)/CN8/RB8 PGEC3/RP15(1)/C
PAGE 7
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Pin Diagrams (Continued) 36-Pin VTLA AVDD AVSS PWM1L/RA3 RMW1H/RA4 34 AN0/RA0 AN1/RA1 35 MCLR AN2/RA2 36 33 32 31 30 29 28 27 PWM2L/RP14(1)/CN14/RB14 AN4/RP9(1)/CN9/RB9 1 26 PWM2H/RP13(1)/CN13/RB13 AN5/RP10(1)/CN10/RB10 2 25 TCK/RP12(1)/CN12/RB12 NC 3 24 TMS/RP11(1)/CN11/RB11 NC 4 23 VDD VDD 5 22 VCAP VSS 6 21 VSS OSCI/CLKI/RP1(1)/CN1/RB1 7 20 N/C OSCO/CLKO/RP2 /CN2/RB2 8 19 PGEC1/SDA1/RP7(1)/CN7/RB7 NC
PAGE 8
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Pin Diagrams (Continued) 36-Pin VTLA Note 1: 2: RMW1H/RA4 33 PWM1L/RA3 AN0/CMP1A/RA0 34 AVSS AN1/CMP1B/RA1 35 MCLR AN2/CMP1C/CMP2A/RA2 36 AVDD AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0 = Pins are up to 5V tolerant 32 31 30 29 28 27 PWM2L/RP14(1)/CN14/RB14 AN4/CMP2C/RP9(1)/CN9/RB9 1 26 PWM2H/RP13(1)/CN13/RB13 AN5/CMP2D/RP10(1)/CN10/RB10 2 25 TCK/RP12(1)/CN12/RB12 NC 3 24 TMS/RP11(1)/CN11/RB11 NC 4 23 VDD VDD 5 22 VCAP VSS 6
PAGE 9
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Pin Diagrams (Continued) 36-Pin VTLA AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0 AN2/CMP1C/CMP2A/RA2 AN1/CMP1B/RA1 AN0/CMP1A/RA0 MCLR AVDD AVSS PWM1L/RA3 RMW1H/RA4 = Pins are up to 5V tolerant 36 35 34 33 32 31 30 29 28 27 PWM2L/RP14(1)/CN14/RB14 1 26 PWM2H/RP13(1)/CN13/RB13 AN5/ISRC3/CMP2D/RP10(1)/CN10/RB10 2 25 TCK/RP12(1)/CN12/RB12 NC 3 24 TMS/RP11(1)/CN11/RB11 NC 4 23 VDD VDD 5 22 VCAP VSS 6 21 VSS OSCI/CLKI/AN6/ISRC2/RP
PAGE 10
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 13 2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers .......................................................................................... 17 3.0 CPU..........................................................................
PAGE 11
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Referenced Sources This device data sheet is based on the following individual chapters of the “dsPIC33F/PIC24H Family Reference Manual”. These documents should be considered the primary reference for the operation of a particular module or device feature. Note: • • • • • • • • • • • • • • • • • • • • • To access the documents listed below, visit the Microchip web site (www.microchip.com). Section 1. “Introduction” (DS70197) Section 2.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 1.0 Note: DEVICE OVERVIEW This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest “dsPIC33F/PIC24H Family Reference Manual” sections.
PAGE 14
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 1-1: dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 BLOCK DIAGRAM PSV and Table Data Access Control Block Y Data Bus X Data Bus Interrupt Controller 16 8 PORTA 16 16 16 Data Latch Data Latch X RAM Y RAM Address Latch Address Latch 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic 23 PORTB 16 23 16 16 Remappable Pins Address Generator Units Address Latch Program Memory EA MUX Data Latch ROM Latch 2
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Type Buffer Type PPS Capable AN0-AN7 I Analog No Analog input channels. CLKI I ST/CMOS No CLKO O — No External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function.
PAGE 16
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type PPS Capable CMP1A CMP1B CMP1C CMP1D CMP2A CMP2B CMP2C CMP2D I I I I I I I I Analog Analog Analog Analog Analog Analog Analog Analog No No No No No No No No Comparator 1 Channel A. Comparator 1 Channel B. Comparator 1 Channel C. Comparator 1 Channel D. Comparator 2 Channel A. Comparator 2 Channel B. Comparator 2 Channel C. Comparator 2 Channel D.
PAGE 17
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
PAGE 18
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 0.1 µF Ceramic R R1 VSS VCAP VDD 10 µF Tantalum VDD MCLR C VDD 0.1 µF Ceramic VSS VSS AVSS VDD AVDD 0.1 µF Ceramic VDD 0.1 µF Ceramic 0.1 µF Ceramic 1: As an option, instead of a hard-wired connection, an inductor (L1) can be substituted between VDD and AVDD to improve ADC noise rejection. The inductor impedance should be less than 1 and the inductor capacity greater than 10 mA.
PAGE 19
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 2.5 ICSP™ Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms.
PAGE 20
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 2.7 Oscillator Value Conditions on Device Start-up If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to 4 MHz < FIN < 8 MHz to comply with device PLL start-up conditions. This means that if the external oscillator frequency is outside of this range, the application must start up in the FRC mode first.
PAGE 21
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 2-4: DIGITAL PFC IPFC VHV_BUS |VAC| k1 k3 VAC k2 ADC Channel FET Driver ADC Channel PWM Output ADC Channel dsPIC33FJ06GS001 FIGURE 2-5: BOOST CONVERTER IMPLEMENTATION IPFC VINPUT VOUTPUT k1 k3 ADC Channel k2 FET Driver ADC Channel PWM Output ADC Channel dsPIC33FJ06GS001  2011-2012 Microchip Technology Inc.
PAGE 22
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 2-6: SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER 12V Input 5V Output k7 ADC Channel FET Driver k1 k2 PWM PWM I5V Analog Comp. ADC Channel dsPIC33FJ06GS202A FIGURE 2-7: INTERLEAVED PFC VOUT+ |VAC| k4 VAC k3 k1 k2 VOUTFET Driver ADC Channel ADC Channel DS75018C-page 22 PWM FET Driver ADC Channel PWM ADC Channel ADC Channel dsPIC33FJ06GS202A  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 2-8: PHASE-SHIFTED FULL-BRIDGE CONVERTER VIN+ Gate 6 Gate 3 Gate 1 VOUT+ S1 S3 VOUT- Gate 2 Gate 4 Gate 5 Gate 6 Gate 5 VIN- FET Driver k2 PWM ADC Channel k1 Analog Ground Gate 1 S1 FET Driver PWM Gate 3 S3 FET Driver ADC Channel dsPIC33FJ09GS302 PWM Gate 2 Gate 4  2011-2012 Microchip Technology Inc.
PAGE 24
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 NOTES: DS75018C-page 24  2011-2012 Microchip Technology Inc.
PAGE 25
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 3.0 CPU 3.1 Data Addressing Overview Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. “CPU” (DS70204) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
PAGE 26
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 3.3 Special MCU Features The 16/16 and 32/16 divide operations are supported, both fractional and integer. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data. A 17-bit by 17-bit single-cycle multiplier is shared by both the MCU ALU and DSP engine.
PAGE 27
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 3-2: PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.
PAGE 28
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 3.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED) bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 00
PAGE 30
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 3-2: U-0 — bit 15 U-0 — R/W-0 SATB Legend: R = Readable bit 0’ = Bit is cleared bit 11 bit 10-8 U-0 — R/W-0 US R/W-0 EDT(1) R-0 R-0 DL<2:0> R-0 bit 8 R/W-0 SATA bit 7 bit 15-13 bit 12 CORCON: CORE CONTROL REGISTER R/W-1 SATDW R/W-0 ACCSAT C = Clearable bit W = Writable bit ‘x = Bit is unknown R/C-0 IPL3(2) R/W-0 PSV R/W-0 RND R/W-0 IF bit 0 -n = Value at POR ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ Unimplemented:
PAGE 31
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 3.5 Arithmetic Logic Unit (ALU) The ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU can affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register.
PAGE 32
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM S a 40 Round t 16 u Logic r a t e 40-Bit Accumulator A 40-Bit Accumulator B 40 Carry/Borrow Out Carry/Borrow In Saturate Adder Negate 40 40 40 16 X Data Bus Barrel Shifter 40 Y Data Bus Sign-Extend 32 Zero Backfill 16 32 33 17-Bit Multiplier/Scaler 16 16 To/From W Array DS75018C-page 32  2011-2012 Microchip Technology Inc.
PAGE 33
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 3.6.1 MULTIPLIER The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value.
PAGE 34
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 The Overflow and Saturation Status bits can optionally be viewed in the STATUS Register (SR) as the logical OR of OA and OB (in bit OAB) and the logical OR of SA and SB (in bit SAB). Programmers can check one bit in the STATUS Register to determine if either accumulator has overflowed, or one bit to determine if either accumulator has saturated. This is useful for complex number arithmetic, which typically uses both accumulators.
PAGE 35
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 3.6.3.2 Data Space Write Saturation In addition to adder/subtracter saturation, writes to data space can also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 NOTES: DS75018C-page 36  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 MEMORY ORGANIZATION Note: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 4. “Program Memory” (DS70203) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
PAGE 38
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.2 All devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 4.2 Data Address Space The CPU has a separate, 16-bit wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps are shown in Figure 4-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This arrangement gives a data space address range of 64 Kbytes or 32K words.
PAGE 40
dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 4-3: DATA MEMORY MAP FOR dsPIC33FJ06GS001/101A/102A DEVICES WITH 256 BYTES OF RAM MSB Address MSb 2-Kbyte SFR Space 256-Byte SRAM Space LSb 0x0000 0x0001 SFR Space 0x07FF 0x0801 0x087F 0x0881 X Data RAM (X) Y Data RAM (Y) 0x07FE 0x0800 0x087E 0x0880 0x08FF 0x0901 0x08FE 0x0900 0x1FFF 0x2001 0x1FFE 0x8001 0x8000 8-Kbyte Near Data Space 0x2000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF DS75018C-page 40 L
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 4-4: DATA MEMORY MAP FOR THE dsPIC33FJ09GS302 DEVICE WITH 1 KB RAM MSB Address MSb 2-Kbyte SFR Space 1-Kbyte SRAM Space LSB Address 16 bits LSb 0x0000 0x0001 SFR Space 0x07FF 0x0801 0x09FF 0x0A01 X Data RAM (X) Y Data RAM (Y) 0x07FE 0x0800 0x09FE 0x0A00 0x0BFF 0x0C01 0x0BFE 0x0C00 0x1FFF 0x2001 0x1FFE 0x8001 0x8000 8-Kbyte Near Data Space 0x2000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF  2011-2012 M
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 4.2.5 X AND Y DATA SPACES The Y data space is used in concert with the X data space by the MAC class of instructions (CLR, ED, EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to provide two concurrent data read paths. The core has two data spaces, X and Y. These data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions).
PAGE 43
Special Function Register Maps TABLE 4-1: SFR Name SFR Addr CPU CORE REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets WREG0 0000 Working Register 0 0000 WREG1 0002 Working Register 1 0000 WREG2 0004 Working Register 2 0000 WREG3 0006 Working Register 3 0000 WREG4 0008 Working Register 4 0000 WREG5 000A Working Register 5 0000 WREG6 000C Working Register 6 0000 WREG7 000E Working Reg
PAGE 44
SFR Name SFR Addr CPU CORE REGISTER MAP (CONTINUED) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 EDT CORCON 0044 — — — US MODCON 0046 XMODEN YMODEN — — Bit 10 Bit 9 Bit 8 DL<2:0> Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SATA SATB SATDW ACCSAT IPL3 PSV RND IF BWM<3:0> YWM<3:0> XWM<3:0> All Resets 0020 0000 XMODSRT 0048 XS<15:1> 0 xxxx XMODEND 004A XE<15:1> 1 xxxx YMODSRT 004C YS<15:1> 0 xxxx YMODEND 004E YE<15:1> 1 xxxx XBREV 0050 BREN DISICNT 0
PAGE 45
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ06GS001 AND dsPIC33FJ06GS101A SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 CNEN1 0060 — — — — — — — — CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CNPU1 0068 — — — — — — — — CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE File Name Legend: Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 0 All Resets CN1IE CN0IE 0000 CN1PUE CN0PUE 0000 Bit 1 x = unknown value on Reset, — = unimplemented, read as ‘0’.
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File Name SFR Addr. INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06GS001 DEVICES ONLY Bit 15 Bit 14 INTCON1 0080 NSTDIS OVAERR INTCON2 0082 ALTIVT DISI Bit 13 Bit 12 Bit 11 Bit 10 OVBERR COVAERR COVBERR OVATE Bit 9 OVBTE Bit 8 Bit 7 Bit 6 Bit 5 COVTE SFTACERR DIV0ERR — — — — — — — — — — Bit 4 Bit 3 MATHERR ADDRERR — — Bit 0 All Reset s Bit 2 Bit 1 STKERR OSCFAIL — 0000 INT2EP INT1EP INT0EP 0000  2011-2012 Microchip Technology Inc.
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File Name INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06GS101A DEVICES ONLY SFR Addr.
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File Name INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06GS102A DEVICES ONLY SFR Addr.
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File Name INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06GS202A DEVICES ONLY SFR Addr.
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File Name INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ09GS302 DEVICES ONLY SFR Addr.
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SFR Name SFR Addr TIMER REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 TMR1 0100 Timer1 Register PR1 0102 Period Register 1 T1CON 0104 TON — TSIDL — — — — — — TMR2 0106 Timer2 Register PR2 010C Period Register 2 T2CON 0110 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
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HIGH-SPEED PWM REGISTER MAP Addr Offset Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 PTCON 0400 PTEN — PTSIDL SESTAT SEIEN EIPU SYNCPOL SYNCOEN SYNCEN — PTCON2 0402 — — — — — — — — — — PTPER 0404 SEVTCMP 0406 File Name Bit 3 Bit 2 SYNCSRC<1:0> — Bit 1 Bit 0 SEVTPS<3:0> — — 040A 041A 0000 FFF8 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
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HIGH-SPEED PWM GENERATOR 2 REGISTER MAP FOR dsPIC33FJ06GS102A, dsPIC33FJ06GS202A AND dsPIC33FJ09GS302 Addr Offset Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 PWMCON2 0440 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN IOCON2 0442 PENH PENL POLH POLL FCLCON2 0444 IFLTMOD PDC2 0446 File Name PMOD<1:0> CLSRC<4:0> Bit 9 Bit 8 ITB MDCS Bit 7 DTC<1:0> OVRENH OVRENL CLPOL Bit 6 OVRDAT<1:0> CLMOD Bit 5 Bit 4 — — FLTDAT<1:0> Bit 2 Bit 1 — CAM XPRES IUE 0000 CLDAT<1:0> S
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HIGH-SPEED PWM GENERATOR 4 REGISTER MAP FOR dsPIC33FJ06GS001, dsPIC33FJ06GS101A AND dsPIC33FJ09GS302 Addr Offset Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 PWMCON4 0480 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN IOCON4 0482 PENH PENL POLH POLL FCLCON4 0484 IFLTMOD PDC4 0486 File Name PMOD<1:0> CLSRC<4:0> Bit 9 Bit 8 ITB MDCS Bit 7 DTC<1:0> OVRENH OVRENL CLPOL Bit 6 OVRDAT<1:0> CLMOD Bit 5 Bit 4 — — FLTDAT<1:0> Bit 2 Bit 1 — CAM XPRES IUE 0000 SWAP OSYNC 0
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I2C1 REGISTER MAP SFR Name SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 I2C1RCV 0200 — — — — — — — — Receive Register I2C1TRN 0202 — — — — — — — — Transmit Register 00FF I2C1BRG 0204 — — — — — — — Baud Rate Generator Register 0000 I2CEN — I2C1CON 0206 I2C1STAT 0208 I2C1ADD 020A — I2C1MSK 020C — Legend: Bit 6 Bit 5 Bit 4 Bit 3 Bit 1 Bit 0 All Resets 0000 IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN S
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File Name ISRCCON Legend: CONSTANT CURRENT SOURCE REGISTER MAP ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 0500 ISRCEN — — — — Bit 10 Bit 9 Bit 8 Bit 6 — — OUTSEL<2:0> Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ISRCCAL<5:0> All Resets 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
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HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ06GS102A AND dsPIC33FJ06GS202A SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 ADCON 0300 ADON — ADSIDL SLOWCLK — GSWTRG — FORM EIE ORDER ADPCFG 0302 — — — — — — — — — — PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 ADSTAT 0306 — — — — — — — — — P6RDY — — — P2RDY P1RDY P0RDY ADBASE 0308 SFR Name Bit 5 Bit 4 SEQSAMP ASYNCSAMP Bit 3 — Bit 2 Bit 1 ADCS<2:0> ADBASE<15:1> ADCPC0 0
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HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ09GS302 SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 ADCON 0300 ADON — ADSIDL SLOWCLK — GSWTRG — ADPCFG 0302 — — — — — — — ADSTAT 0306 — — — — — — — ADBASE 0308 SFR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 FORM EIE ORDER — PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 — — P6RDY — — P3RDY P2RDY P1RDY P0RDY SEQSAMP ASYNCSAMP Bit 2 — Bit 1 Bit 0 ADCS<2:0> ADBASE<15:1> All Resets
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SFR Name PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33FJ06GS001 SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 — — Bit 11 Bit 10 Bit 9 Bit 8 — — Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets — — — — — — — — 3F00 — — — — — — 3F00 — — 3F00 RPINR0 0680 — — RPINR1 0682 — — RPINR2 0684 — — RPINR3 0686 — — — — RPINR29 06BA — — FLT1R<5:0> — — RPINR30 06BC — — FLT3R<5:0> — — FLT2R<5:0> 3F3F RPINR31 06BE — — FLT5R<5:0> — — FLT4R<5
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SFR Name PERIPHERAL PIN SELECT INPUT REGISTER MAP FOR dsPIC33FJ06GS202A AND dsPIC33FJ09GS302 SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 — — Bit 11 Bit 10 Bit 9 Bit 8 — — Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets — — — — — — — — 3F00 — — — — — — 3F00 RPINR0 0680 — — RPINR1 0682 — — RPINR2 0684 — — RPINR3 0686 — — — — — — — — — — T2CKR<5:0> 003F RPINR7 068E — — — — — — — — — — IC1R<5:0> 003F RPINR11 0696 — — — — — — —
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File Name PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ06GS102A, dsPIC33FJ06GS202A AND dsPIC33FJ09GS302 Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets RPOR0 06D0 — — RP1R<5:0> — — RP0R<5:0> 0000 RPOR1 06D2 — — RP3R<5:0> — — RP2R<5:0> 0000 RPOR2 06D4 — — RP5R<5:0> — — RP4R<5:0> 0000 RPOR3 06D6 — — RP7R<5:0> — — RP6R<5:0> 0000 RPOR4 06D8 — — RP9R<5:0> — — RP8R<5:0> 0
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PORTA REGISTER MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISA 02C0 — — — — — — — — — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 001F PORTA 02C2 — — — — — — — — — — — RA4 RA3 RA2 RA1 RA0 xxxx LATA 02C4 — — — — — — — — — — — LATA4 LATA3 LATA2 LATA1 LATA0 0000 ODCA 02C6 — — — — — — — — — — — ODCA4 ODCA3 — — — 0000 SFR Name Legend: x =
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SYSTEM CONTROL REGISTER MAP SFR Name SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets RCON 0740 TRAPR IOPUWR — — — — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR xxxx(1) OSCCON 0742 — CLKLOCK IOLOCK LOCK — CF — — OSWEN 0300(2) CLKDIV 0744 ROI PLLFBD 0746 — — — — — — — — — — — — — COSC<2:0> — DOZE<2:0> DOZEN OSCTUN 0748 — LFSR 074C — REFOCON 074E ROON
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SFR Name PMD REGISTER MAP FOR dsPIC33FJ06GS001 SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 PMD1 0770 — — — T2MD PMD3 0774 — — — — PMD4 0776 — — — PMD6 077A — — — PMD7 077C — — — Legend: Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T1MD — PWMMD — I2C1MD — — — — — — ADCMD 0000 — CMPMD — — — — — — — — — — 0000 — — — — — — — — — REFOMD — — — 0000 — PWM4MD — — PWM1MD — — — — — — — — 0000 — — — CM
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SFR Name PMD REGISTER MAP FOR dsPIC33FJ06GS202A SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 PMD1 0770 — — — T2MD T1MD — PMD2 0772 — — — — — — PMD3 0774 — — — — — CMPMD PMD4 0776 — — — — — — PMD6 077A — — — — — — PMD7 077C — — — — — — CMP2MD Legend: Bit 1 Bit 0 All Resets — — ADCMD 0000 — — OC1MD 0000 — — — — 0000 — REFOMD — — — 0000 — — — — — 0000 — — — — — — 0000 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bi
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 4.3.1 4.4 SOFTWARE STACK In addition to its use as a working register, the W15 register in the devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It predecrements for stack pops and postincrements for stack pushes, as shown in Figure 4-5.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 4-39: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode File Register Direct Description The address of the File register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the Effective Address (EA). Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 4.5 Modulo Addressing 4.5.1 Modulo Addressing mode is a method used to provide an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many DSP algorithms. Modulo Addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both).
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 4.5.3 MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register. Address boundaries check for addresses equal to: XB<14:0> is the Bit-Reversed Address modifier, or ‘pivot point,’ which is typically a constant. In the case of an FFT computation, its value is equal to half of the FFT data buffer size.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 4-7: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer TABLE 4-40: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address A3 A2 A1 A0 Bit-Reversed Address Decimal A3 A2 A1 A0 Decima
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 4.7 Interfacing Program and Data Memory Spaces 4.7.1 Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. The device architecture uses a 24-bit wide program space and a 16-bit wide data space.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 4-8: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) Program Counter 0 0 23 bits EA Table Operations(2) 1/0 1/0 TBLPAG 8 bits 16 bits 24 bits Select Program Space Visibility(1) (Remapping) 0 1 EA 0 PSVPAG 8 bits 15 bits 23 bits User/Configuration Space Select Byte Select Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 4.7.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 4.7.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to stored constant data from the data space without the need to use special instructions (such as TBLRDL or TBLRDH).
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 5.0 FLASH PROGRAM MEMORY pin pairs: PGECx/PGEDx), and three other lines for power (VDD), ground (VSS) and Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 5.2 RTSP Operation The dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one word at a time. Table 25-12 shows typical erase and programming times.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 5.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Key Register bits (write-only) DS75018C-page 78 x = Bit i
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 6.0 RESETS A simplified block diagram of the Reset module is shown in Figure 6-1. Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 6.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED) bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred Note 1: 2: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 6.2 System Reset A warm Reset is the result of all the other Reset sources, including the RESET instruction. On warm Reset, the device will continue to operate from the current clock source, as indicated by the Current Oscillator Selection bits (COSC<2:0>) in the Oscillator Control register (OSCCON<14:12>). There are two types of Reset: • Cold Reset • Warm Reset A cold Reset is the result of a Power-on Reset (POR) or a Brown-out Reset (BOR).
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 6-2: SYSTEM RESET TIMING VBOR VPOR VDD TPOR POR 1 TBOR 2 BOR 3 TPWRT SYSRST 4 Oscillator Clock TOSCD TOST TLOCK 6 TFSCM FSCM 5 Reset Device Status Run Time Note 1: 2: 3: 4: 5: 6: POR: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until VDD crosses the VPOR threshold and the delay, TPOR, has elapsed.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 6.3 Power-on Reset (POR) A Power-on Reset (POR) circuit ensures the device is reset from power-on. The POR circuit is active until VDD crosses the VPOR threshold and the delay, TPOR, has elapsed. The delay, TPOR, ensures the internal device bias circuits become stable. The device supply voltage characteristics must meet the specified starting voltage and rise rate requirements to generate the POR. Refer to Section 25.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 6.5 External Reset (EXTR) The external Reset is generated by driving the MCLR pin low. The MCLR pin is a Schmitt trigger input with an additional glitch filter. Reset pulses that are longer than the minimum pulse width will generate a Reset. Refer to Section 25.0 “Electrical Characteristics” for minimum pulse width specifications. The external Reset (MCLR) pin (EXTR) bit in the Reset Control (RCON) register is set to indicate the MCLR Reset. 6.5.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 6.10 Using the RCON Status Bits The user application can read the Reset Control (RCON) register after any device Reset to determine the cause of the Reset. Note: Table 6-3 provides a summary of the Reset flag bit operation. The status bits in the RCON register should be cleared after they are read so that the next RCON register value, after a device Reset, will be meaningful.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 7.0 INTERRUPT CONTROLLER Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 41. “Interrupts (Part IV)” (DS70300) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com).
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Decreasing Natural Order Priority FIGURE 7-1: Note 1: DS75018C-page 88 dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 ~ ~ ~ Interrupt Vect
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 7-1: INTERRUPT VECTORS Vector Number Interrupt Request (IQR) IVT Address 8 0 0x000014 AIVT Address Interrupt Source Highest Natural Order Priority 0x000114 INT0 – External Interrupt 0 9 1 0x000016 0x000116 IC1 – Input Capture 1 10 2 0x000018 0x000118 OC1 – Output Compare 1 11 3 0x00001A 0x00011A T1 – Timer1 12-14 4-6 0x00001C-0x000020 15 7 0x000022 0x000122 T2 – Timer2 0x00011C-0x000120 Reserved 16 8 0x000024 0
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 7.3 Interrupt Control and Status Registers The following registers are implemented for the interrupt controller: • • • • • • INTCON1 INTCON2 IFSx IECx IPCx INTTREG 7.3.1 INTCON1 AND INTCON2 Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit as well as the control and status flags for the processor trap sources.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-1: SR: CPU STATUS REGISTER(1) R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R-0 R/W-0 OA OB SA SB OAB SAB DA DC bit 15 bit 8 R/W-0(3) R/W-0(3) R/W-0(3) IPL<2:0>(2) R-0 R/W-0 R/W-0 R/W-0 R/W-0 RA N OV Z C bit 7 bit 0 Legend: C = Clearable bit U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown IPL<2:0>: CPU Interrupt Priority
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bi
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Uses alternate
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-5: U-0 IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 — — R/W-0 ADIF R/W-0 (1) U1TXIF R/W-0 (1) U1RXIF R/W-0 SPI1IF (1) R/W-0 U-0 (1) SPI1EIF — bit 15 bit 8 R/W-0 U-0 T2IF U-0 — — U-0 R/W-0 — T1IF R/W-0 (1) OC1IF R/W-0 IC1IF R/W-0 (2) INT0IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemente
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — INT2IF — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT1IF CNIF AC1IF(1 MI2C1IF SI2C1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IF: External I
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-7: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — PSEMIF — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 Unimplemented: Read as ‘0’ bit 9 PSEMIF: PWM Special Event Match Interrupt Flag Status b
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-9: IFS5: INTERRUPT FLAG STATUS REGISTER 5 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 PWM2IF(1) PWM1IF — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — JTAGIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 PWM2IF: PWM2 Interrupt Flag Status bit(1) 1 = Interrupt request has occurred
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-10: IFS6: INTERRUPT FLAG STATUS REGISTER 6 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 ADCP1IF ADCP0IF — — — — — — bit 15 bit 8 R/W-0 AC2IF U-0 (1) U-0 — — U-0 — U-0 — U-0 — R/W-0 U-0 (2) PWM4IF bit 7 — bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADCP1IF: ADC Pair 1 Conversion Done Interrupt Flag Status bit 1 =
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-11: IFS7: INTERRUPT FLAG STATUS REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 — — — ADCP6IF — — ADCP3IF(1) ADCP2IF(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4 ADCP6IF: ADC
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-12: U-0 IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 — — R/W-0 ADIE R/W-0 (1) U1TXIE R/W-0 (1) U1RXIE R/W-0 (1) SPI1IE R/W-0 U-0 (1) SPI1EIE — bit 15 bit 8 R/W-0 U-0 T2IE U-0 — — U-0 — R/W-0 T1IE R/W-0 (1) OC1IE R/W-0 (2) IC1IE R/W-0 INT0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplement
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-13: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — INT2IE — — — — — bit 15 bit 8 U-0 U-0 — — U-0 — R/W-0 INT1IE R/W-0 CNIE R/W-0 (1) AC1IE R/W-0 R/W-0 MI2C1IE SI2C1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IE: Externa
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-14: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — PSEMIE — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 Unimplemented: Read as ‘0’ bit 9 PSEMIE: PWM Special Event Match Interrupt Enable bi
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-16: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 PWM2IE(1) PWM1IE — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — JTAGIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 PWM2IE: PWM2 Interrupt Enable bit(1) 1 = Interrupt request is enabled 0
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-17: IEC6: INTERRUPT ENABLE CONTROL REGISTER 6 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 ADCP1IE ADCP0IE — — — — — — bit 15 bit 8 R/W-0 U-0 AC2IE(1) U-0 — — U-0 — U-0 — U-0 — R/W-0 U-0 (2) PWM4IE bit 7 — bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADCP1IE: ADC Pair 1 Conversion Done Interrupt Enable bit 1 = Int
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-18: IEC7: INTERRUPT ENABLE CONTROL REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — U-0 — R/W-0 ADCP6IE U-0 U-0 — — R/W-0 ADCP3IE R/W-0 (1) ADCP2IE(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-5 Unimplemented: Read as ‘0’ bit 4 ADCP6IE: ADC Pair 6 Conversion
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-19: U-0 IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 R/W-1 — R/W-0 R/W-0 T1IP<2:0> U-0 R/W-1 — R/W-0 OC1IP<2:0> R/W-0 (1) bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 (2) — IC1IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 INT0IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Tim
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-20: U-0 IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 R/W-1 — R/W-0 R/W-0 T2IP<2:0> U-0 U-0 U-0 U-0 — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111 = I
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-21: U-0 IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 R/W-1 R/W-0 R/W-0 U1RXIP<2:0>(1) — U-0 R/W-1 R/W-0 R/W-0 SPI1IP<2:0>(1) — bit 15 bit 8 U-0 R/W-1 R/W-0 SPI1EIP<2:0>(1) — R/W-0 U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-22: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 ADIP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 U1TXIP<2:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 ADIP<2:0>: ADC1 Conversion Complete
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-23: U-0 IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 R/W-1 — R/W-0 R/W-0 CNIP<2:0> U-0 R/W-1 R/W-0 R/W-0 AC1IP<2:0>(1) — bit 15 bit 8 U-0 R/W-1 — R/W-0 MI2C1IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 SI2C1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Chang
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-24: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 INT1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bi
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-26: IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 R/W-0 PSEMIP<2:0> U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 PSEMIP<2:0>: PWM Specia
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-28: IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 JTAGIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 JTAGIP<2:0>: JTAG Interrupt Priority bits 1
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-29: U-0 IPC23: INTERRUPT PRIORITY CONTROL REGISTER 23 R/W-1 R/W-0 R/W-0 U-0 PWM2IP(1) — R/W-1 — R/W-0 R/W-0 PWM1IP<2:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 PWM2IP<2:0>: PWM2 Interrupt Priority
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-30: IPC24: INTERRUPT PRIORITY CONTROL REGISTER 24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 (1) — PWM4IP U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 PWM4IP<2:0>: PWM4 Interrupt Priority bits(1
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-31: U-0 IPC25: INTERRUPT PRIORITY CONTROL REGISTER 25 R/W-1 R/W-0 R/W-0 AC2IP<2:0>(1) — U-0 U-0 U-0 U-0 — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 AC2IP<2:0>: Analog Comparator 2 Interrupt P
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-32: U-0 IPC27: INTERRUPT PRIORITY CONTROL REGISTER 27 R/W-1 — R/W-0 R/W-0 ADCP1IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 ADCP0IP<2:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 ADCP1IP<2:0>:
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-33: IPC28: INTERRUPT PRIORITY CONTROL REGISTER 28 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 (1) — ADCP3IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 (2) ADCP2IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 ADCP3IP<2:0>: ADC Pair
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-34: IPC29: INTERRUPT PRIORITY CONTROL REGISTER 29 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 ADCP6IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 ADCP6IP<2:0>: ADC Pair
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 7-35: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 U-0 — — — — R-0 R-0 R-0 R-0 ILR<3:0> bit 15 bit 8 U-0 R-0 R-0 — R-0 R-0 R-0 R-0 R-0 VECNUM<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits 1111 = CPU I
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 7.4 Interrupt Setup Procedures 7.4.1 7.4.3 INITIALIZATION Complete the following steps to configure an interrupt source at initialization: 1. 2. Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 OSCILLATOR CONFIGURATION The oscillator system provides: • External and internal oscillator options as clock sources • An on-chip Phase Lock Loop (PLL) to scale the internal operating frequency to the required system clock frequency • An internal FRC oscillator that can also be used with the PLL, thereby allowing full-speed operation without any external clock generation hardware • Clock switching between various clock sources • Programmable clock postsc
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 8.1 CPU Clocking System output frequencies for device operation. PLL configuration is described in Section 8.1.3 “PLL Configuration”. The devices provide six system clock options: • • • • • • Fast RC (FRC) Oscillator FRC Oscillator with PLL Primary (XT, HS or EC) Oscillator Primary Oscillator with PLL Low-Power RC (LPRC) Oscillator FRC Oscillator with Postscaler 8.1.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 8.1.3 PLL CONFIGURATION • If PLLPOST<1:0> = 00, then N2 = 2. This provides a FOSC of 160/2 = 80 MHz. The resultant device operating speed is 80/2 = 40 MIPS. The primary oscillator and internal FRC oscillator can optionally use an on-chip PLL to obtain higher speeds of operation. The PLL provides significant flexibility in selecting the device operating speed. A block diagram of the PLL is shown in Figure 8-2.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 8.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER(1,3) (CONTINUED) bit 4 Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Detect bit (read/clear by application) 1 = FSCM has detected clock failure 0 = FSCM has not detected clock failure bit 2-1 Unimplemented: Read as ‘0’ bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete Note 1: 2: 3: Writes to this
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 8-2: R/W-0 CLKDIV: CLOCK DIVISOR REGISTER(2) R/W-0 ROI R/W-1 R/W-1 R/W-0 R/W-0 DOZEN(1) DOZE<2:0> R/W-0 R/W-0 FRCDIV<2:0> bit 15 bit 8 R/W-0 R/W-1 PLLPOST<1:0> U-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 PLLPRE<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = In
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 8-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — PLLDIV8 bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 PLLDIV<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV<8:0>: PLL Feedback D
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 8-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER(2) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 (1) — TUN<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1) 011111 =
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 ACLKCON: AUXILIARY CLOCK DIVISOR CONTROL REGISTER(1) REGISTER 8-5: R/W-0 R-0 R/W-1 U-0 U-0 ENAPLL APLLCK SELACLK — — R/W-1 R/W-1 R/W-1 APSTSCLR<2:0>(2) bit 15 bit 8 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 ASRCSEL FRCSEL — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ENAPLL: Auxiliary
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 8-6: R/W-0 REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER U-0 ROON — R/W-0 ROSSLP R/W-0 R/W-0 R/W-0 ROSEL R/W-0 RODIV<3:0> R/W-0 (1) bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — bit 7 U-0 — bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ROON: Reference Oscillator Output Enable bit 1 = Reference oscilla
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 8-7: U-0 LFSR: LINEAR FEEDBACK SHIFT REGISTER R/W-0 R/W-0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 LFSR<14:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LFSR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-0 LFSR<14:0>: Pseudo Random FRC Trim Value bits  2011-2012
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 8.5 Clock Switching Operation Applications are free to switch among any of the four clock sources (primary, LP, FRC and LPRC) under software control at any time. To limit the possible side effects of this flexibility, devices have a safeguard lock built into the switch process. Note: 8.5.1 Primary Oscillator mode has three different submodes (XT, HS and EC), which are determined by the POSCMD<1:0> Configuration bits.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 8.6 Fail-Safe Clock Monitor (FSCM) 8.7 The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate, even in the event of an oscillator failure. The FSCM function is enabled by programming. If the FSCM function is enabled, the LPRC internal oscillator runs at all times (except during Sleep mode) and is not subject to control by the Watchdog Timer.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 NOTES: DS75018C-page 136  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 9.0 POWER-SAVING FEATURES Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 9. “Watchdog Timer (WDT) and Power-Saving Modes” (DS70196) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 9.2.2 IDLE MODE The following occur in Idle mode: • The CPU stops executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9.4 “Peripheral Module Disable”). • If the WDT or FSCM is enabled, the LPRC also remains active.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 9.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 9-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — IC1MD(1) bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — OC1MD(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-9 Unimplemented: Read as ‘0’ bit 8 IC1MD: Input Capture 1 Module Dis
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 9-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 — — — — — CMPMD(1) — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10 CMPMD: Analog Comparator Module Disable
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 9-5: U-0 PMD6: PERIPHERAL MODULE DISABLE CONTROL REGISTER 6 U-0 — — U-0 — U-0 — R/W-0 U-0 (1) PWM4MD — R/W-0 PWM2MD R/W-0 (2) PWM1MD bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11 PWM4MD: PWM Generator 4 M
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 9-6: U-0 PMD7: PERIPHERAL MODULE DISABLE CONTROL REGISTER 7 U-0 — — U-0 — U-0 — U-0 — U-0 — R/W-0 R/W-0 (1) CMP2MD CMP1MD(1) bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 Unimplemented: Read as ‘0’ bit 9 CMP2MD: Analog Comparator 2 Module
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 9-7: PMD8: PERIPHERAL MODULE DISABLE CONTROL REGISTER 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — CCSMD(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-2 Unimplemented: Read as ‘0’ bit 1 CCSMD: Constant Current Source Module Disa
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 10.0 I/O PORTS Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 10. “I/O Ports” (DS70193) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com).
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 10-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Peripheral Module Output Multiplexers Peripheral Input Data I/O Peripheral Module Enable Peripheral Output Enable 1 Output Enable 0 Peripheral Output Data PIO Module WR TRIS Output Data 0 Read TRIS Data Bus 1 D Q I/O Pin CK TRIS Latch D WR LAT + WR PORT Q CK Data Latch Read LAT Input Data Read PORT DS75018C-page 146  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 10.2 Open-Drain Configuration In addition to the PORT, LAT and TRIS registers for data control, some digital only port pins can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 10.6 Peripheral Pin Select (PPS) Peripheral Pin Select configuration enables peripheral set selection and placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, programmers can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device. The Peripheral Pin Select configuration feature operates over a fixed subset of digital I/O pins.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 10-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION) Function Name Register Configuration Bits INT1 RPINR0 INT1R<5:0> External Interrupt 2 INT2 RPINR1 INT2R<5:0> Timer1 External Clock T1CK RPINR2 T1CKR<5:0> Timer2 External Clock T2CK RPINR3 T2CKR<5:0> IC1 RPINR7 IC1R<5:0> Input Name External Interrupt 1 Input Capture 1 Output Compare Fault A OCFA RPINR11 OCFAR<5:0> UART1 Receive U1RX RPINR18 U1RXR<5:0> UART1 Clear-t
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 10.6.2.2 Output Mapping FIGURE 10-3: In contrast to inputs, the outputs of the Peripheral Pin Select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 10.6.2.3 Virtual Pins Four virtual RPn pins (RP32, RP33, RP34 and RP35) are supported, which are identical in functionality to all other RPn pins, with the exception of pinouts. These four pins are internal to the devices and are not connected to a physical device pin. These pins provide a simple way for inter-peripheral connection without utilizing a physical pin.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 10.7 1. 2. In some cases, certain pins, as defined in Table 25-9 under “Injection Current”, have internal protection diodes to VDD and VSS. The term, “Injection Current”, is also referred to as “Clamp Current”. On designated pins, with sufficient external current limiting precautions by the user, I/O pin input voltages are allowed to be greater or less than the data sheet absolute maximum ratings with respect to the VSS and VDD supplies.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 10.9 Peripheral Pin Select Registers The following registers are implemented for remappable peripheral configuration: Not all Output Remappable Peripheral registers are implemented on all devices. See the register description of the specific register for further details. • 15 Input Remappable Peripheral Registers • 19 Output Remappable Peripheral Registers Note: Input and output register values can only be changed if IOLOCK (OSCCON<6>) = 0.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 INT2R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 INT2R<5:0>: Assign Externa
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-3: RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 T1CKR<5:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 T1CKR<5:0>: Assign Timer
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-4: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 T2CKR<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 T2CKR<5:0>: Assign Timer2
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-5: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IC1R<5:0>(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 IC1R<5:0>: Assign Input
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-6: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OCFAR<5:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 OCFAR<5:0>: Assign Ou
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-7: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U1CTSR<5:0>(1) bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U1RXR<5:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U1CTSR<5:
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-8: U-0 RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 — R/W-1 R/W-1 — R/W-1 R/W-1 SCK1R<5:0> R/W-1 R/W-1 (1) bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SDI1R<5:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 SCK1R<5:0>
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-9: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SS1R<5:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 SS1R<5:0>: Assign SPI1
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-10: RPINR29: PERIPHERAL PIN SELECT INPUT REGISTER 29 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLT1R<5:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FLT1R<5:0>: Assign PWM
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-11: RPINR30: PERIPHERAL PIN SELECT INPUT REGISTER 30 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLT3R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLT2R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FLT3R<5:0>: Assig
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-12: RPINR31: PERIPHERAL PIN SELECT INPUT REGISTER 31 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLT5R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLT4R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FLT5R<5:0>: Assig
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-13: RPINR32: PERIPHERAL PIN SELECT INPUT REGISTER 32 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLT7R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLT6R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FLT7R<5:0>: Assig
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-14: RPINR33: PERIPHERAL PIN SELECT INPUT REGISTER 33 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SYNCI1R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLT8R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 SYNCI1R<5:0>: A
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-15: RPINR34: PERIPHERAL PIN SELECT INPUT REGISTER 34 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SYNCI2R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 SYNCI2R<5:0>: Assign PW
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-16: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP1R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP0R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP1R<5:0>: Peripheral
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-18: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP5R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP4R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP5R<5:0>: Peripheral
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-20: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP9R<5:0>(1) bit 15 bit 8 U-0 U-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 (1) — RP8R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP9R<5:0>: Pe
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-22: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP13R<5:0>(1) bit 15 bit 8 U-0 U-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 (1) — RP12R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP13R<5:0>:
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 10-24: RPOR16: PERIPHERAL PIN SELECT OUTPUT REGISTER 16 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP33R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP32R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP33R<5:0>: Perip
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 11.0 TIMER1 The unique features of Timer1 allow it to be used for Real-Time Clock applications. A block diagram of Timer1 is shown in Figure 11-1. Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 11.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 11.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 12.0 TIMER2 FEATURES In Timer and Gated Timer modes, the input clock is derived from the internal instruction cycle clock (FCY). In Synchronous Counter mode, the input clock is derived from the external clock input at the TxCK pin. Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 12.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 13.0 INPUT CAPTURE Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 12. “Input Capture” (DS70198) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com).
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 13.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 14.0 OUTPUT COMPARE output pulse, or a sequence of output pulses, by changing the state of the output pin on the compare match events. The output compare module can also generate interrupts on compare match events. Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 14.1 Output Compare Modes application must disable the associated timer when writing to the Output Compare Control registers to avoid malfunctions. Configure the Output Compare modes by setting the appropriate Output Compare Mode (OCM<2:0>) bits in the Output Compare Control (OC1CON<2:0>) register. Table 14-1 lists the different bit settings for the Output Compare modes. Figure 14-2 illustrates the output compare operation for various modes.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 14.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 NOTES: DS75018C-page 182  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 15.0 HIGH-SPEED PWM Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 43. “High-Speed PWM” (DS70323) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com).
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 15.2 Feature Description The PWM module is designed for applications that require: • High-resolution at high PWM frequencies • The ability to drive Standard, Edge-Aligned, Center-Aligned Complementary mode, and Push-Pull mode outputs • The ability to create multiphase PWM outputs For Center-Aligned mode, the duty cycle, period, phase and dead-time resolutions will be 8.32 ns. Two common, medium power converter topologies are push-pull and half-bridge.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 15-1: SIMPLIFIED CONCEPTUAL BLOCK DIAGRAM OF HIGH-SPEED PWM PWMCONx Pin and Mode Control LEBCONx Control for Blanking External Input Signals TRGCONx ADC Trigger Control Dead-Time Control ALTDTRx, DTRx PWM Enable and Mode Control PTCON MDC Master Duty Cycle Register PDC1 MUX Latch PWM Generator 1 Comparator Channel 1 Dead-Time Generator PWM1H Channel 2 Dead-Time Generator PWM2H PWM1L Timer 16-Bit Data Bus MUX Latch PWM Generator
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 15-2: PARTITIONED OUTPUT PAIR, COMPLEMENTARY PWM MODE Phase Offset TMRx < PDC Timer/Counter PWM Override Logic Dead-Time Logic M U X PWMXH M U X PWMXL Duty Cycle Comparator PWM Duty Cycle Register Channel Override Values Fault Override Values Fault Pin 15.3 Fault Pin Assignment Logic PWM Control Registers The following registers control the operation of the high-speed PWM module.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-1: R/W-0 PTEN bit 15 R/W-0 (1) bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5-4 bit 3-0 Note 1: R/W-0 HS/HC-0 R/W-0 R/W-0 — PTSIDL SESTAT SEIEN EIPU(1) U-0 R/W-0 R/W-0 R/W-0 R/W-0 SYNCSRC<1:0>(1) R/W-0 R/W-0 SYNCPOL(1) SYNCOEN(1) bit 8 R/W-0 R/W-0 SEVTPS<3:0>(1) bit 0 Legend: R = Readable bit -n = Value at POR bit 14 bit 13 U-0 — SYNCEN bit 7 bit 15 PTCON: PWM TIME BASE CONTROL REGISTER HC = Hardware Cl
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-2: PTCON2: PWM CLOCK DIVIDER SELECT REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 PCLKDIV<2:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 PCLKDIV<2:0>: PWM Inp
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-4: R/W-0 SEVTCMP: PWM SPECIAL EVENT COMPARE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP <15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP <7:3> U-0 U-0 U-0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 SEVTCMP<15:3>: Special Event Compare Count Value bits bit 2-0 Unimplemented
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-6: HS/HC-0 PWMCONx: PWMx CONTROL REGISTER HS/HC-0 FLTSTAT(1) CLSTAT (1) HS/HC-0 TRGSTAT R/W-0 FLTIEN R/W-0 CLIEN R/W-0 R/W-0 (3) TRGIEN ITB R/W-0 MDCS(3) bit 15 bit 8 R/W-0 R/W-0 DTC<1:0> U-0 — U-0 — U-0 — R/W-0 CAM (2,3) R/W-0 (4) XPRES R/W-0 IUE bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-6: PWMCONx: PWMx CONTROL REGISTER (CONTINUED) bit 2 CAM: Center-Aligned Mode Enable bit(2,3) 1 = Center-Aligned mode is enabled 0 = Center-Aligned mode is disabled bit 1 XPRES: External PWM Reset Control bit(4) 1 = Current-limit source resets time base for this PWM generator if it is in Independent Time Base mode 0 = External pins do not affect PWM time base bit 0 IUE: Immediate Update Enable bit 1 = Updates to the active MDC/PDCx/SDCx
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-7: R/W-0 PDCx: PWMx GENERATOR DUTY CYCLE REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDCx<15:8>(2) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDCx<7:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: 2: x = Bit is unknown PDCx<15:0>: PWMx Generator # Duty Cycle Value bits(
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-9: R/W-0 PHASEx: PWMx PRIMARY PHASE SHIFT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEx<15:8>(1,2) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEx<7:0>(1,2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: 2: x = Bit is unknown PHASEx<15:0>: PWMx Phase Shift Value or Indep
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-10: SPHASEx: PWMx SECONDARY PHASE SHIFT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPHASEx<15:8>(1,2) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPHASEx<7:0>(1,2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 Note 1: 2: x = Bit is unknown SPHASEx<15:0>: Secondary Phase Offset f
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 .
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-13: TRGCONx: PWMx TRIGGER CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 TRGDIV<3:0> U-0 U-0 U-0 U-0 — — — — bit 15 bit 8 R/W-0 U-0 DTM(1) — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSTRT<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 TRGDIV<3:0>: Trigger # Output Divider bits 1111 = Tri
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-14: IOCONx: PWMx I/O CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 PENH PENL POLH POLL R/W-0 R/W-0 PMOD<1:0>(1) R/W-0 R/W-0 OVRENH OVRENL bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 FLTDAT<1:0>(2) OVRDAT<1:0> R/W-0 R/W-0 CLDAT<1:0>(2) R/W-0 R/W-0 SWAP OSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-14: IOCONx: PWMx I/O CONTROL REGISTER (CONTINUED) bit 3-2 CLDAT<1:0>: State for PWMxH and PWMxL Pins if CLMODE is Enabled bits(2) IFLTMOD (FCLCONx<15>) = 0, Normal Fault mode: If current-limit is active, then CLDAT<1> provides the state for PWMxH. If current-limit is active, then CLDAT<0> provides the state for PWMxL. IFLTMOD (FCLCONx<15>) = 1, Independent Fault mode: CLDAT<1:0> is ignored.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-15: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CLSRC<4:0>(2,3) IFLTMOD R/W-0 R/W-0 CLPOL(1) CLMOD bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTSRC<4:0>(2,3) R/W-0 R/W-0 FLTPOL(1) R/W-0 FLTMOD<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-15: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER (CONTINUED) FLTSRC<4:0>: Fault Control Signal Source Select for PWM Generator # bits(2,3) 11111 = Reserved • • • 01000 = Reserved bit 7-3 00111 = Fault 8 00110 = Fault 7 00101 = Fault 6 00100 = Fault 5 00011 = Fault 4 00010 = Fault 3 00001 = Fault 2 00000 = Fault 1 bit 2 FLTPOL: Fault Polarity for PWMx Generator # bit(1) 1 = The selected Fault source is active-low 0 = The selected Fault
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-16: TRIGx: PWMx PRIMARY TRIGGER COMPARE VALUE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGCMP<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGCMP<7:3> U-0 U-0 U-0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 TRGCMP<15:3>: Trigger Control Value bits When primary
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-18: LEBCONx: PWMx LEADING-EDGE BLANKING CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHR PHF PLR PLF FLTLEBEN CLLEBEN R/W-0 R/W-0 LEB<6:5> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEB<4:0> U-0 U-0 U-0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PHR: PWMxH Rising Ed
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-19: PWMCAPx: PRIMARY PWMx TIME BASE CAPTURE REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 PWMCAP<15:8>(1,2) bit 15 bit 8 R-0 R-0 R-0 PWMCAP<7:3> R-0 R-0 (1,2) U-0 U-0 U-0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 PWMCAP<15:3>: Captured PWM Time Base Value bits(1,2) The value in this
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 15-21: AUXCONx: PWMx AUXILIARY CONTROL REGISTER R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 UW-0 HRPDIS HRDDIS — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 CHOPSEL<3:0> R/W-0 R/W-0 R/W-0 CHOPHEN CHOPLEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 HRPDIS: High-Resolution PWMx Period D
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 16.0 SERIAL PERIPHERAL INTERFACE (SPI) Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 18. “Serial Peripheral Interface (SPI)” (DS70206) of the “dsPIC33F/ PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 16.1 1. In Frame mode, if there is a possibility that the master may not be initialized before the slave: a) If FRMPOL (SPIxCON2<13>) = 1, use a pull-down resistor on SSx. b) If FRMPOL = 0, use a pull-up resistor on SSx. Note: 2.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 16.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DISSCK DISSDO MODE16 SMP CKE(1) bit 15 bit 8 R/W-0 R/W-0 SSEN(3) CKP R/W-0 R/W-0 MSTEN R/W-0 R/W-0 R/W-0 SPRE<2:0>(2) R/W-0 PPRE<1:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplem
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)(2) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 • • • 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)(2) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: 2: 3: This bit is not used in Framed SPI modes.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 16-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 FRMEN SPIFSD FRMPOL — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — FRMDLY — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support en
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 17.0 INTER-INTEGRATED CIRCUIT™ (I2C™) Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 19. “Inter-Integrated Circuit (I2C™)” (DS70195) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 17-1: I2C™ BLOCK DIAGRAM Internal Data Bus I2C1RCV SCL1 Read Shift Clock I2C1RSR LSb SDA1 Address Match Match Detect Write I2C1MSK Write Read I2C1ADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2C1STAT Collision Detect Read Write I2C1CON Acknowledge Generation Read Clock Stretching Write I2C1TRN LSb Read Shift Clock Reload Control BRG Down Counter Write I2C1BRG Read TCY/2 DS75018C-page
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 17.2 I2C Registers • I2C1TRN is the transmit register to which bytes are written during a transmit operation • The I2C1ADD register holds the slave address • A status bit, ADD10, indicates 10-Bit Address mode • The I2C1BRG acts as the Baud Rate Generator (BRG) reload value I2C1CON and I2C1STAT are control and status registers, respectively. The I2C1CON register is readable and writable. The lower six bits of I2C1STAT are read-only.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 17-1: I2C1CON: I2C1 CONTROL REGISTER (CONTINUED) bit 8 SMEN: SMBus Input Levels bit 1 = Enables I/O pin thresholds compliant with SMBus specification 0 = Disables SMBus input thresholds bit 7 GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enables interrupt when a general call address is received in the I2C1RSR (module is enabled for reception) 0 = General call address is disabled bit 6 STREN: SCL1 Clock Stretch Enable bit
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 17-2: I2C1STAT: I2C1 STATUS REGISTER R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HSC R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC IWCOL I2COV D_A P S R_W RBF TBF bit 7 bit 0 Legend: HS = Hardware Settable bit’ HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 17-2: I2C1STAT: I2C1 STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop is detected.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 17-3: I2C1MSK: I2C1 SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0 R/W-0 AMSK<9:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 AMSK<9:0>: Mask for
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 NOTES: DS75018C-page 218  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 18.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com).
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 18.1 1. 2. UART Helpful Tips In multinode, direct-connect UART networks, UART receive inputs react to the complementary logic level defined by the URXINV bit (U1MODE<4>), which defines the Idle state, the default of which is logic high, (i.e., URXINV = 0).
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 18.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 18-1: U1MODE: UART1 MODE REGISTER (CONTINUED) bit 4 URXINV: Receive Polarity Inversion bit(3) 1 = U1RX Idle state is ‘0’ 0 = U1RX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit(3) 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits(3) 11 = 9-bit data, no parity 10 = 8-bit data, odd pa
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 18-2: R/W-0 U1STA: UART1 STATUS AND CONTROL REGISTER R/W-0 UTXISEL1(2) UTXINV (2) R/W-0 UTXISEL0 U-0 (2) R/W-0, HC (2) — UTXBRK R/W-0 (1,2) UTXEN R-0 R-1 (2) UTXBF TRMT(2) bit 15 bit 8 R/W-0 R/W-0 URXISEL<1:0>(2) R/W-0 (2) ADDEN R-1 RIDLE R-0 (2) R-0 (2) PERR R/C-0 (2) FERR (2) OERR R-0 URXDA(2) bit 7 bit 0 Legend: HC = Hardware Clearable bit C = Clearable bit R = Readable bit W = Writable bit U = Unimplemen
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 18-2: U1STA: UART1 STATUS AND CONTROL REGISTER (CONTINUED) bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bits(2) 11 = Interrupt is set on U1RSR transfer, making the receive buffer full (i.e., has 4 data characters) 10 = Interrupt is set on U1RSR transfer, making the receive buffer 3/4 full (i.e.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 19.0 HIGH-SPEED 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 44. “High-Speed 10-Bit ADC” (DS70321) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available on the Microchip web site (www.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 19-1: ADC BLOCK DIAGRAM FOR THE dsPIC33FJ06GS001 DEVICE Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits Eight 16-Bit Registers Bus Interface SAR Core AN12(1) (EXTREF) Data Format AN0 AN1 Shared Sample-and-Hold AN2 AN3 AN6 AN7 AN13(2) (INTREF) Note 1: To measure the voltage at AN12 (EXTREF), an analog comparator must be enabled and EXTREF must be selected as the comparator reference.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 19-2: ADC BLOCK DIAGRAM FOR THE dsPIC33FJ06GS101A DEVICE Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits AN0 Eight 16-Bit Registers Bus Interface SAR Core Data Format AN2 AN1 AN3 Shared Sample-and-Hold AN6 AN7  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 19-3: ADC BLOCK DIAGRAM FOR dsPIC33FJ06GS102A DEVICE Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits AN0 Eight 16-Bit Registers Bus Interface SAR Core Data Format AN2 AN1 AN3 Shared Sample-and-Hold AN4 AN5 DS75018C-page 228  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 19-4: ADC BLOCK DIAGRAM FOR dsPIC33FJ06GS202A DEVICE Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits AN0 SAR Core Eight 16-Bit Registers Bus Interface AN12(1) (EXTREF) Data Format AN2 AN1 AN3 Shared Sample-and-Hold AN4 AN5 AN13(2) (INTREF) Note 1: To measure the voltage at AN12 (EXTREF), an analog comparator must be enabled and EXTREF must be selected as the comparator reference.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 19-5: ADC BLOCK DIAGRAM FOR dsPIC33FJ09GS302 DEVICE Even Numbered Inputs with Dedicated Sample-and-Hold (S&H) Circuits AN0 SAR Core Eight 16-Bit Registers Bus Interface AN12(1) (EXTREF) Data Format AN2 AN1 AN3 Shared Sample-and-Hold AN4 AN5 AN6 AN7 AN13(2) (INTREF) Note 1: To measure the voltage at AN12 (EXTREF), an analog comparator must be enabled and EXTREF must be selected as the comparator reference.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 19.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 19-1: ADCON: ADC CONTROL REGISTER (CONTINUED) bit 8 FORM: Data Output Format bit(1) 1 = Fractional (DOUT = dddd dddd dd00 0000) 0 = Integer (DOUT = 0000 00dd dddd dddd) bit 7 EIE: Early Interrupt Enable bit(1) 1 = Interrupt is generated after first conversion is completed 0 = Interrupt is generated after second conversion is completed bit 6 ORDER: Conversion Order bit(1) 1 = Odd numbered analog input is converted first, followed by convers
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 19-2: ADSTAT: ADC STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/C-0, HS U-0 U-0 R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS — P6RDY — — P3RDY(1) P2RDY(2) P1RDY P0RDY bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unk
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 19-3: R/W-0 ADBASE: ADC BASE REGISTER(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 (2) ADBASE<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADBASE<7:1>(2) U-0 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-1 ADBASE<15:1>: ADC Base Register bits(2) This register contains the base
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 19-4: ADPCFG: ADC PORT CONFIGURATION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 PCFG7(1) PCFG6 (1) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 19-5: ADCPC0: ADC CONVERT PAIR CONTROL REGISTER 0 R/W-0 IRQEN1 bit 15 R/W-0 PEND1 R/W-0 IRQEN0 bit 7 R/W-0 PEND0 bit 14 bit 13 bit 12-8 Note 1: R/W-0 R/W-0 R/W-0 TRGSRC1<4:0> R/W-0 R/W-0 bit 8 R/W-0 SWTRG0 R/W-0 R/W-0 R/W-0 TRGSRC0<4:0> R/W-0 R/W-0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15 R/W-0 SWTRG1 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 19-5: bit 7 bit 6 bit 5 bit 4-0 Note 1: ADCPC0: ADC CONVERT PAIR CONTROL REGISTER 0 (CONTINUED) IRQEN0: Interrupt Request Enable 0 bit 1 = Enables IRQ generation when requested conversion of channels AN1 and AN0 is completed 0 = IRQ is not generated PEND0: Pending Conversion Status 0 bit 1 = Conversion of channels AN1 and AN0 is pending; set when selected trigger is asserted 0 = Conversion is complete SWTRG0: Software Trigger 0 bit 1 = Star
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 19-6: ADCPC1: ADC CONVERT PAIR CONTROL REGISTER 1 R/W-0 IRQEN3(1) bit 15 R/W-0 PEND3(1) R/W-0 IRQEN2(2) bit 7 R/W-0 PEND2(2) bit 14 bit 13 bit 12-8 R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC3<4:0>(1) R/W-0 bit 8 R/W-0 SWTRG2(2) R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC2<4:0>(2) R/W-0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15 R/W-0 SWTRG3(1) W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = B
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 19-6: bit 7 bit 6 bit 5 bit 4-0 ADCPC1: ADC CONVERT PAIR CONTROL REGISTER 1 (CONTINUED) IRQEN2: Interrupt Request Enable 2 bit(2) 1 = Enables IRQ generation when requested conversion of channels AN5 and AN4 is completed 0 = IRQ is not generated PEND2: Pending Conversion Status 2 bit(2) 1 = Conversion of channels AN5 and AN4 is pending; set when selected trigger is asserted.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 19-7: ADCPC3: ADC CONVERT PAIR CONTROL REGISTER 3(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 IRQEN6 PEND6 SWTRG6 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC6<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 IRQEN
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 19-7: bit 4-0 ADCPC3: ADC CONVERT PAIR CONTROL REGISTER 3(1) (CONTINUED) TRGSRC6<4:0>: Trigger 6 Source Selection bits Selects trigger source for conversion of analog channels AN13 and AN12.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 NOTES: DS75018C-page 242  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 20.0 HIGH-SPEED ANALOG COMPARATOR • • • • DACOUT pin to provide DAC output DACOUT amplifier (1x, 1.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 20.3 Module Applications This module provides a means for the SMPS dsPIC DSC devices to monitor voltage and currents in a power conversion application. The ability to detect transient conditions and stimulate the dsPIC DSC processor and/or peripherals, without requiring the processor and ADC to constantly monitor voltages or currents, frees the dsPIC DSC to perform other tasks.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 20.8 Hysteresis 20.9 An additional feature of the module is hysteresis control. Hysteresis can be enabled or disabled and its amplitude can be controlled by the HYSSEL<1:0> bits in the CMPCONx register. Three different values are available: 15 mV, 30 mV and 45 mV. It is also possible to select the edge (rising or falling) to which hysteresis is to be applied.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 20-1: R/W-0 CMPCONx: COMPARATOR CONTROL x REGISTER U-0 CMPON(1) — R/W-0 CMPSIDL R/W-0 (1) R/W-0 (1) HYSSEL<1:0> R/W-0 FLTREN R/W-0 (1) FCLKSEL R/W-0 (1) DACOE(1) bit 15 bit 8 R/W-0 R/W-0 INSEL<1:0>(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EXTREF(1) HYSPOL(1) CMPSTAT(1) HGAIN(1) CMPPOL(1) RANGE(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit i
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 20-1: CMPCONx: COMPARATOR CONTROL x REGISTER (CONTINUED) bit 5 EXTREF: Enable External Reference bit(1) 1 = External source provides reference to DAC (maximum DAC voltage determined by external voltage source) 0 = Internal reference sources provide reference to DAC (maximum DAC voltage determined by RANGE bit setting) bit 4 HYSPOL: Comparator Hysteresis Polarity Select bit(1) 1 = Hysteresis is applied to the falling edge of the comparator ou
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 20-2: CMPDACx: COMPARATOR DAC CONTROL x REGISTER U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0 R/W-0 CMREF<9:8>(1) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CMREF<7:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 CMREF<9:0>: Comp
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 21.0 CONSTANT CURRENT SOURCE Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 19. “Inter-Integrated Circuit (I2C™)” (DS70195) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com).
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 21.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 22.0 SPECIAL FEATURES Configuration Bits Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 24. “Programming and Diagnostics” (DS70207) and Section 25.
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Address CONFIGURATION FLASH BYTES FOR dsPIC33FJ06GS001/101A/X02A DEVICES Name Bits 23-8 Bit 7 — — 000FF0 FICD — Reserved(1) 000FF4 FWDT — FWDTEN 000FF6 FOSC — 000FF8 FOSCSEL — IESO 000FFA FGS — — Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 JTAGEN Reserved(2) — — OSCIOFNC Bit 1 Bit 0 ICS<1:0> PLLKEN WDTPRE IOL1WAY — — — — — — — — — — — GCP GWRP Bit 1 Bit 0 FCKSM<1:0> WDTPOST<3:0> POSCMD<1:0> FNOSC<2:0> Legend: — = unimplemented, read as ‘1’.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 REGISTER 22-1: CONSTANT CURRENT SOURCE CALIBRATION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R-0 R-0 R-0 R-0 R-0 R-0 CCSCAL<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 23
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 22-3: dsPIC33F CONFIGURATION BITS DESCRIPTION Bit Field Description GCP General Segment Code-Protect bit 1 = User program memory is not code-protected 0 = Code protection is enabled for the entire program memory space GWRP General Segment Write-Protect bit 1 = User program memory is not write-protected 0 = User program memory is write-protected IESO Two-Speed Oscillator Start-up Enable bit 1 = Start up device with FRC, then automatically sw
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 22-3: dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Description PLLKEN PLL Lock Enable bit 1 = Clock switch to PLL source will wait until the PLL lock signal is valid 0 = Clock switch will not wait for the PLL lock signal JTAGEN JTAG Enable bit 1 = JTAG is enabled 0 = JTAG is disabled ICS<1:0> ICD Communication Channel Select bits 11 = Communicate on PGEC1 and PGED1 10 = Communicate on PGEC2 and PGED2 01 = Communicate on PGE
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 22.2 On-Chip Voltage Regulator The devices power their core digital logic at a nominal 2.5V. This can create a conflict for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator provides power to the core from the other VDD pins.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 22.4 Watchdog Timer (WDT) 22.4.2 The Watchdog Timer (WDT) is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. 22.4.1 PRESCALER/POSTSCALER The nominal WDT clock source from LPRC is 32 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the WDTPRE Configuration bit (FWDT<4>).
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 22.5 JTAG Interface 22.7 In-Circuit Debugger A JTAG interface is implemented, which supports boundary scan device testing, as well as in-circuit programming. Detailed information on this interface will be provided in future revisions of this document. The dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 devices provide simple debugging functionality through the PGECx (Emulation/ Debug Clock) and PGEDx (Emulation/Debug Data) pin functions. 22.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 23.0 Note: INSTRUCTION SET SUMMARY This data sheet summarizes the features of the dsPIC33FJ06GS001/101A/102A/ 202A and dsPIC33FJ09GS302 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest “dsPIC33F/PIC24H Family Reference Manual” sections.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Most instructions are a single word. Certain double-word instructions are designed to provide all the required information in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. The double-word instructions execute in two instruction cycles.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 23-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wm*Wm Multiplicand and Multiplier Working register pair for Square instructions  {W4 * W4,W5 * W5,W6 * W6,W7 * W7} Wm*Wn Multiplicand and Multiplier Working register pair for DSP instructions  {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7} Wn One of 16 Working registers {W0..W15} Wnd One of 16 Destination Working registers {W0...
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 23-2: Base Instr # 1 2 3 4 INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR Assembly Syntax # of # of Words Cycles Description Status Flags Affected ADD Acc Add Accumulators 1 1 ADD f f = f + WREG 1 1 OA,OB,SA,SB C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 23-2: Base Instr # 10 11 12 13 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTSC BTSS BTST BTSTS Assembly Syntax Description # of # of Words Cycles Status Flags Affected BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 (2 or 3) None BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 (2 or 3) None BTSS f,#bit4 Bit Test f, Skip if Set 1 1 (2 or 3) None BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 (2 or 3) None BTST f,
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 23-2: Base Instr # 29 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic DIV Assembly Syntax # of # of Words Cycles Description Status Flags Affected DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 23-2: Base Instr # 48 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic MPY Assembly Syntax Description # of # of Words Cycles Status Flags Affected MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 49 MPY.N MPY.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 23-2: Base Instr # 66 67 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic RRNC SAC Assembly Syntax # of # of Words Cycles Description Status Flags Affected RRNC f f = Rotate Right (No Carry) f 1 1 RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z N,Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None SAC.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 24.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 24.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 24.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 24.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 24.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 25.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 25.1 DC Characteristics TABLE 25-1: OPERATING MIPS vs. VOLTAGE Maximum MIPS Characteristic VDD Range (in Volts) — VBOR-3.6V(1) -40°C to +85°C 40 — VBOR-3.6V(1) -40°C to +125°C 40 Note 1: Temp Range (in °C) dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules, such as the ADC, etc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS DC CHARACTERISTICS Param. Symbol Characteristic Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Min. Typ.(1) Max. Units VBOR — 3.6 V Conditions Operating Voltage DC10 VDD Supply Voltage(4) DC12 VDR RAM Data Retention Voltage(2) 1.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Param. Typical(1) Operating Current Max.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Param. Typical(1) Max.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Param. Typical(1) Max.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Param. Typical(1) Max.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Param. Symbol VIL Characteristic Min. Typ.(1) Max. Units Conditions Input Low Voltage DI10 I/O Pins VSS — 0.2 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 I/O Pins with OSC1 VSS — 0.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Param.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Param. Symbol DO10 DO20 VOL VOH DO20A VOH1 Note 1: Characteristic Min. Typ. Max. Units Output Low Voltage I/O Pins: 4x Sink Driver Pins – RA0-RA2, RB0-RB2, RB5-RB10, RB15 — — 0.4 V IOL  6 mA, VDD = 3.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-12: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS Param. Symbol Characteristic Min. Typ.(1) Max. Units Conditions Program Flash Memory D130 EP Cell Endurance 10,000 — — D131 VPR VDD for Read VMIN — 3.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 25.2 AC Characteristics and Timing Parameters This section defines dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 AC characteristics and timing parameters. TABLE 25-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Operating voltage VDD range as described in Table 25-1.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-2: EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 OS30 OS30 Q4 OSC1 OS20 OS31 OS31 OS25 CLKO OS41 OS40 TABLE 25-16: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param. Symbol OS10 FIN Min. Typ.(1) Max.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param. Symbol Characteristic Min. Typ.(1) Max. Units OS50 FPLLI PLL Voltage Controlled Oscillator (VCO) Input Frequency Range 0.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-19: AC CHARACTERISTICS: INTERNAL FRC ACCURACY AC CHARACTERISTICS Param. Characteristic Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA +85°C for industrial -40°C  TA  +125°C for Extended Min. Typ. Max. Units Conditions Internal FRC Accuracy @ FRC Frequency = 7.37 MHz (1) F20a FRC -2 — +2 % -40°C  TA +85°C VDD = 3.0-3.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-3: I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 25-1 for load conditions. TABLE 25-21: I/O TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param. DO31 DO32 Symbol TIOR TIOF Min. Typ.(1) Max.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-4: VDD RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS SY12 MCLR SY10 Internal POR PWRT Time-out SY11 SY30 OSC Time-out Internal Reset Watchdog Timer Reset SY20 SY13 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure 25-1 for load conditions. TABLE 25-22: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-5: TIMER1 AND TIMER2 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 OS60 Tx20 TMRx Note: Refer to Figure 25-1 for load conditions. TABLE 25-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-24: TIMER2 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param. Symbol Characteristic Min. Typ. Max.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-6: INPUT CAPTURE (CAP1) TIMING CHARACTERISTICS IC1 IC10 IC11 IC15 Note: Refer to Figure 25-1 for load conditions. TABLE 25-25: INPUT CAPTURE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Characteristic(1) Param.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-8: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA OC15 Active OC1 Tri-State TABLE 25-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS AC CHARACTERISTICS Param. Symbol Characteristic(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Min. Typ. Max.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-9: HIGH-SPEED PWM MODULE FAULT TIMING CHARACTERISTICS MP30 FLTx MP20 PWMx FIGURE 25-10: HIGH-SPEED PWM MODULE TIMING CHARACTERISTICS MP11 MP10 PWMx Note: Refer to Figure 25-1 for load conditions. TABLE 25-28: HIGH-SPEED PWM MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-29: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY Standard Operating Conditions: 3.0V to 3.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-12: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx LSb SP30, SP31 Note: Refer to Figure 25-1 for load conditions. TABLE 25-30: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-13: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx SP30, SP31 SP40 SDIx LSb MSb In LSb In Bit 14 - - - -1 SP41 Note: Refer to Figure 25-1 for load conditions. TABLE 25-31: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-14: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING CHARACTERISTICS SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 SP30, SP31 SDIx MSb In LSb Bit 14 - - - - - -1 MSb SDOx SP30, SP31 LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 25-1 for load conditions. TABLE 25-32: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-15: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDIx MSb In Bit 14 - - - -1 SP51 LSb In SP41 SP40 Note: Refer to Figure 25-1 for load conditions.  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-33: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-16: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 SP52 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDIx MSb In Bit 14 - - - -1 SP51 LSb In SP41 SP40 Note: Refer to Figure 25-1 for load conditions.  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-34: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-17: SPIx SLAVE MODE (FULL-DUPLEX CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX Bit 14 - - - - - -1 LSb SP51 SP30,SP31 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 25-1 for load conditions.  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-35: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-18: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX Bit 14 - - - - - -1 LSb SP51 SP30,SP31 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 25-1 for load conditions.  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-36: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param No.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-19: I2C1 BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCL1 IM31 IM34 IM30 IM33 SDA1 Start Condition Stop Condition Note: Refer to Figure 25-1 for load conditions. FIGURE 25-20: I2C1 BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCL1 IM11 IM26 IM10 IM25 IM33 SDA1 In IM40 IM40 IM45 SDA1 Out Note: Refer to Figure 25-1 for load conditions.  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-37: I2C1 BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Min.(1) Max.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 FIGURE 25-21: I2C1 BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCL1 IS34 IS31 IS30 IS33 SDA1 Start Condition FIGURE 25-22: Stop Condition I2C1 BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCL1 IS30 IS26 IS31 IS25 IS33 SDA1 In IS40 IS40 IS45 SDA1 Out  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-38: I2C1 BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS Param. Symbol IS10 IS11 IS20 IS21 IS25 TLO:SCL THI:SCL TF:SCL TR:SCL TSU:DAT Characteristic Clock Low Time Clock High Time SDA1 and SCL1 Fall Time SDA1 and SCL1 Rise Time Data Input Setup Time Min. Max.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 = TABLE 25-39: 10-BIT HIGH-SPEED ADC MODULE SPECIFICATIONS Standard Operating Conditions: 3.0V and 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended AC CHARACTERISTICS(2) Param. Symbol Characteristic Min. Typ. Max. Units Conditions Device Supply AD01 AVDD Module VDD Supply — — — — AVDD is internally connected to VDD on 18-pin and 28-pin devices.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-39: 10-BIT HIGH-SPEED ADC MODULE SPECIFICATIONS (CONTINUED) AC CHARACTERISTICS Param. Standard Operating Conditions: 3.0V and 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended (2) Symbol Characteristic Min. Typ. Max.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-41: HIGH-SPEED ANALOG COMPARATOR MODULE SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Operating temperature: -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended DC CHARACTERISTICS(2) Param. Symbol Characteristic Min. Typ. Max.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-43: DAC OUTPUT (DACOUT PIN) DC SPECIFICATIONS DC CHARACTERISTICS(1) Standard Operating Conditions (unless otherwise stated) Operating temperature: -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Param. Symbol Characteristic DA11 — DA12 DA13 DA14 DA15 Min.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 TABLE 25-45: CONSTANT CURRENT SOURCE SPECIFICATIONS DC CHARACTERISTICS Param. Symbol Characteristic CC01 IDD CC02 IREG CC03 IOUT Note 1: Standard Operating Conditions (unless otherwise stated) Operating temperature: -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended (1) Min. Typ. Max.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 NOTES: DS75018C-page 314  2011-2012 Microchip Technology Inc.
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DC AND AC DEVICE CHARACTERISTICS GRAPHS Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. FIGURE 26-1: VOH – 4x DRIVER PINS FIGURE 26-3: 0.040 -0.
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FIGURE 26-7: TYPICAL IPD CURRENT @ VDD = 3.3V 450 90 400 85 IDD Current (mA) IPD Current (µA) 350 300 250 200 150 80 75 70 65 100 60 50 55 0 TYPICAL IDD CURRENT @ VDD = 3.3V, +25ºC 50 -40 -20 0 20 40 60 80 100 10 120 15 20 Temperature (Celsius) FIGURE 26-6: 25 30 35 40 MIPS TYPICAL IDOZE CURRENT @ VDD = 3.3V TYPICAL IIDLE CURRENT @ VDD = 3.3V, +25ºC FIGURE 26-8: 40 20 35 18 16 IIDLE Current (mA)  2011-2012 Microchip Technology Inc.
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TYPICAL FRC FREQUENCY @ VDD = 3.3V 7.38 32.6 32.55 LPRC Frequency (kHz) 7.36 FRC Frequency (MHz) TYPICAL LPRC FREQUENCY @ VDD = 3.3V FIGURE 26-11: 7.34 7.32 7.3 32.5 32.45 32.4 32.35 32.3 7.28 -40 -20 0 20 40 60 Temperature (Celsius) 7.26 -40 -20 0 20 40 60 80 100 120 100 120 Temperature (Celsius) FIGURE 26-10: TYPICAL INTREF @ VDD = 3.3V 1.25 1.24 1.24 INTREF (V) 1.23 1.23 1.22 1.22 DS75018C-page 317 1.21 1.21 1.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 NOTES: DS75018C-page 318  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 27.0 PACKAGING INFORMATION 27.1 Package Marking Information 18-Lead PDIP Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 18-Lead SOIC (.300”) dsPIC30F3012 30I/P e3 0610017 Example XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX dsPIC33FJ06 GS101-I/SO YYWWNNN 0830235 20-Lead SSOP Example XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Legend: XX...
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 27.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 27.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS75018C-page 322  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS75018C-page 324  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 /HDG 3ODVWLF 6KULQN 6PDOO 2XWOLQH 66 ± PP %RG\ >6623@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D N E E1 NOTE 1 1 2 e b c A2 A φ A1 L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV L 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ± ± 2YHUD
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS75018C-page 326  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 /HDG 3ODVWLF 6KULQN 6PDOO 2XWOLQH 66 ± PP %RG\ >6623@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D N E E1 1 2 NOTE 1 b e c A2 A φ A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ± ± 2YHUD
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS75018C-page 328  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS75018C-page 330  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 /HDG 6NLQQ\ 3ODVWLF 'XDO ,Q /LQH 63 ± PLO %RG\ >63',3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV ,1&+(6 0,1 1 120 0$; 3LWFK H 7RS WR 6HDWLQJ 3ODQH $ ± ± 0ROGHG 3DFNDJH 7KLFNQHVV $ %DVH WR 6HDWLQJ 3ODQH $
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 DS75018C-page 334  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 00 ± [ [ PP %RG\ >4)1 6@ ZLWK PP &RQWDFW /HQJWK 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 DS75018C-page 336  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 NOTES: DS75018C-page 338  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 APPENDIX A: REVISION HISTORY This is the initial released version of this document. Where applicable, new sections were added to each peripheral chapter that provide information and links to related resources, as well as helpful tips. For examples, see Section 18.1 “UART Helpful Tips” and Section 18.1 “UART Helpful Tips”. Revision B (February 2012) The data sheet status was updated from Advance Information to Preliminary.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Revision C (August 2012) This revision includes minor typographical updates and content corrections. Major changes include new figures in Section 26.0 “DC and AC Device Characteristics Graphs”, updated values in Table 25-39 in Section 25.0 “Electrical Characteristics” and updated package drawings in Section 27.0 “Packaging Information”. DS75018C-page 340  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 INDEX A C AC Characteristics ............................................................ 282 Internal LPRC Accuracy............................................ 285 Internal RC Accuracy ................................................ 285 Load Conditions ........................................................ 282 Temperature and Voltage Specifications .................. 282 Alternate Interrupt Vector Table (AIVT) ..............................
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 DC Specifications DAC Output (DACOUT Pin) ...................................... 312 Development Support ....................................................... 267 Doze Mode........................................................................ 138 DSC Guidelines................................................................... 17 Basic Connection Requirements................................. 17 Decoupling Capacitors ...................................
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 P Packaging ......................................................................... 319 Details ....................................................................... 321 Marking ..................................................................... 319 Peripheral Module Disable (PMD) .................................... 138 Peripheral Pin Select (PPS) .............................................. 148 Registers..........................................
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 RPINR7 (Peripheral Pin Select Input 7) .................... 157 RPOR0 (Peripheral Pin Select Output 0) .................. 168 RPOR1 (Peripheral Pin Select Output 1) .................. 168 RPOR16 (Peripheral Pin Select Output 16) .............. 172 RPOR17 (Peripheral Pin Select Output 17) .............. 172 RPOR2 (Peripheral Pin Select Output 2) .................. 169 RPOR3 (Peripheral Pin Select Output 3) ..................
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 Output Compare (OC1)............................................. 290 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer ............................... 287 SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) ........................................... 296 SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) ........................................... 295 SPIx Master Mode (Half-Duplex, Transmit Only, CKE = 0) ..................
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 NOTES: DS75018C-page 346  2011-2012 Microchip Technology Inc.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC 33 FJ 06 GS0 01 T - E / SP - XXX Examples: a) dsPIC33FJ06GS001-I/SS: SMPS dsPIC33, 6-Kbyte program memory, 20-pin, Industrial temp.,SSOP package.
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dsPIC33FJ06GS001/101A/102A/202A and dsPIC33FJ09GS302 NOTES: DS75018C-page 350  2011-2012 Microchip Technology Inc.
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Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.