Datasheet

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
DS70318F-page 92 © 2008-2012 Microchip Technology Inc.
6.2 Power-on Reset (POR)
A Power-on Reset (POR) circuit ensures the device is
reset from power-on. The POR circuit is active until
V
DD crosses the VPOR threshold and the delay, TPOR,
has elapsed. The delay, TPOR, ensures the internal
device bias circuits become stable.
The device supply voltage characteristics must meet
the specified starting voltage and rise rate
requirements to generate the POR. Refer to
Section 24.0 “Electrical Characteristics” for details.
The POR status (POR) bit in the Reset Control
(RCON<0>) register is set to indicate the Power-on
Reset.
6.2.1 Brown-out Reset (BOR) and
Power-up Timer (PWRT)
The on-chip regulator has a Brown-out Reset (BOR)
circuit that resets the device when the VDD is too low
(VDD < VBOR) for proper device operation. The BOR
circuit keeps the device in Reset until V
DD crosses the
VBOR threshold and the delay, TBOR, has elapsed. The
delay, TBOR, ensures the voltage regulator output
becomes stable.
The BOR status (BOR) bit in the Reset Control
(RCON<1>) register is set to indicate the Brown-out
Reset.
The device will not run at full speed after a BOR as the
V
DD should rise to acceptable levels for full-speed
operation. The PWRT provides power-up time delay
(T
PWRT) to ensure that the system power supplies have
stabilized at the appropriate levels for full-speed
operation before the SYSRST
is released.
The power-up timer delay (T
PWRT) is programmed by
the Power-on Reset Timer Value Select
(FPWRT<2:0>) bits in the POR Configuration
(FPOR<2:0>) register, which provides eight settings
(from 0 ms to 128 ms). Refer to Section 21.0 “Special
Features” for further details.
Figure 6-3 shows the typical brown-out scenarios. The
reset delay (T
BOR + TPWRT) is initiated each time VDD
rises above the VBOR trip point.
FIGURE 6-3: BROWN-OUT SITUATIONS
VDD
SYSRST
VBOR
V
DD
SYSRST
VBOR
V
DD
SYSRST
VBOR
T
BOR + TPWRT
VDD dips before PWRT expires
T
BOR + TPWRT
TBOR + TPWRT