Datasheet
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
DS70318F-page 372 © 2008-2012 Microchip Technology Inc.
Revision E (December 2009)
The revision includes the following global update:
• Added Note 2 to the shaded table that appears at
the beginning of each chapter. This new note
provides information regarding the availability of
registers and their associated bits
This revision also includes minor typographical and
formatting changes throughout the data sheet text.
All other major changes are referenced by their
respective section in the following table.
TABLE A-3: MAJOR SECTION UPDATES
Section Name Update Description
“16-bit Microcontrollers and Digital
Signal Controllers (up to 16 KB Flash
and up to 2 KB SRAM) with High-
Speed PWM, ADC and Comparators”
Changed CN6 to CN5 on pin 16 of dsPIC33FJ16GS502 28-pin SPDIP,
SOIC pin diagram.
Section 2.0 “Guidelines for Getting
Started with 16-bit Digital Signal
Controllers”
Removed the 10 Ohm resistor from Figure 2-1.
Section 4.0 “Memory Organization” Renamed bit 13 of the REFOCON SFR in the System Control Register
Map from ROSIDL to ROSSLP and changed the All Resets value from
‘0000’ to ‘2300’ for the ACLKCON SFR (see 4-41).
Section 8.0 “Oscillator Configuration” Updated the default reset values from R/W-0 to R/W-1 for the SELACLK
and APSTSCLR<2:0> bits in the ACLKCON register (see Register 8-5).
Renamed the ROSIDL bit to ROSSLP in the REFOCON register (see
Register 8-6).
Section 9.0 “Power-Saving Features” Updated the last paragraph of Section 9.2.2 “Idle Mode” to clarify when
instruction execution begins.
Added Note 1 to the PMD1 register (see Register 9-1).
Section 10.0 “I/O Ports” Changed the reference to digital-only pins to 5V tolerant pins in the
second paragraph of Section 10.2 “Open-Drain Configuration”.
Section 15.0 “High-Speed PWM” Updated the smallest pulse width value from 0x0008 to 0x0009 in Note 1
of the shaded note that follows the MDC register (see Register 15-5).
Updated the smallest pulse width value from 0x0008 to 0x0009 and the
maximum pulse width value from 0x0FFEF to 0x0008 in Note 2 of the
shaded note that follows the PDCx and SDCx registers (see Register 15-7
and Register 15-8).
Added Note 2 and updated the FLTDAT<1:0> and CLDAT<1:0> bits,
changing the word ‘data’ to ‘state’ in the IOCONx register (see
Register 15-14).
Section 18.0 “Universal
Asynchronous Receiver Transmitter
(UART)”
Updated the two baud rate range features to: 10 Mbps to 38 bps at 40
MIPS.
Section 19.0 “High-Speed 10-bit
Analog-to-Digital Converter (ADC)”
Updated Note 1 in the ADCPC0 register (see Register 19-5).
Updated Note 3 in the ADCPC1 register (see Register 19-6).
Updated Note 2 in the ADCPC2 and ADCPC3 registers (see Register 19-
7 and Register 19-8).