Datasheet

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
DS70318F-page 300 © 2008-2012 Microchip Technology Inc.
TABLE 24-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise
stated)
Operating temperature -40°C ≤ T
A ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol Characteristic Min Typ
(1)
Max Units Conditions
OS50 FPLLI PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range
0.8 — 8 MHz ECPLL, XTPLL modes
OS51 FSYS On-Chip VCO System
Frequency
100 — 200 MHz —
OS52 TLOCK PLL Start-up Time (Lock Time) 0.9 1.5 3.1 mS —
OS53 D
CLK CLKO Stability (Jitter)
(2)
-3 0.5 3 % Measured over 100 ms
period
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested in manufacturing.
2: These parameters are characterized by similarity, but are not tested in manufacturing. This specification is
based on clock cycle by clock cycle measurements. To calculate the effective jitter for individual time bases
or communication clocks use this formula:
TABLE 24-18: AUXILIARY PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V)
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise
stated)
Operating temperature -40°C ≤ T
A ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
Param
No.
Symbol Characteristic Min Typ
(1)
Max Units Conditions
OS56 F
HPOUT 0n-Chip 16x PLL CCO
Frequency
112 118 120 MHz
—
OS57 FHPIN On-Chip 16x PLL Phase
Detector Input Frequency
7.0 7.37 7.5 MHz —
OS58 TSU Frequency Generator Lock
Time
——10µs —
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested in manufacturing.
Peripheral Clock Jitter
D
CLK
FOSC
Peripheral Bit Rate Clock
--------------------------------------------------------------
⎝⎠
⎛⎞
------------------------------------------------------------------------
=
For example: Fosc = 32 MHz, DCLK = 3%, SPI bit rate clock, (i.e., SCK) is 2 MHz.
SPI SCK Jitter
D
CLK
32 MHz
2 MHz
--------------------
⎝⎠
⎛⎞
------------------------------
3%
16
----------
3%
4
--------
0.75%====