Datasheet
© 2008-2012 Microchip Technology Inc. DS70318F-page 293
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
TABLE 24-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for
Extended
Param
No.
Symbol Characteristic Min Typ
(1)
Max Units Conditions
VIL Input Low Voltage
DI10 I/O Pins V
SS —0.2VDD V—
DI15 MCLR
VSS —0.2VDD V
—
DI16 I/O Pins with OSC1 VSS —0.2VDD V—
DI18 I/O Pins with SDAx, SCLx V
SS — 0.3 VDD V SMbus disabled
DI19 I/O Pins with SDAx, SCLx V
SS — 0.8 V SMbus enabled
V
IH Input High Voltage
DI20
DI21
I/O Pins Not 5V Tolerant
(4)
I/O Pins 5V Tolerant
(4)
0.7 VDD
0.7 VDD
—
—
VDD
5.5
V
V
DI28
DI29
SDA1, SCL1
SDA1, SCL1
0.7 VDD
2.1
—
—
5.5
5.5
V
V
SMbus disabled
SMbus enabled
I
CNPU CNx Pull-up Current
DI30 — 250 — μAVDD = 3.3V, VPIN = VSS
IIL Input Leakage Current
(2,3,4)
DI50 I/O Pins with:
4x Driver Pins - RA0-RA2, RB0-
RB2, RB5-RB10, RB15, RC1, RC2,
RC9, RC10
8x Driver Pins - RC0, RC3-RC8,
RC11-RC13
16x Driver Pins - RA3, RA4, RB3,
RB4, RB11-RB14
—
—
—
—
—
—
±2
±4
±8
μA
μA
μA
V
SS ≤ VPIN ≤ VDD,
Pin at high-impedance
V
SS ≤ VPIN ≤ VDD,
Pin at high-impedance
VSS ≤ VPIN ≤ VDD,
Pin at high-impedance
DI55 MCLR ——±2μAVSS ≤ VPIN ≤ VDD
DI56 OSC1 — — ±2 μAVSS ≤ VPIN ≤ VDD,
XT and HS modes
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2: The leakage current on the MCLR
pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: See “Pin Diagrams” for the list of 5V tolerant I/O pins.
5: V
IL source < (VSS – 0.3). Characterized but not tested.
6: Non-5V tolerant pins V
IH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not
tested.
7: Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V.
8: Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts.
9: Any number and/or combination of I/O pins not excluded under I
ICL or IICH conditions are permitted pro-
vided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.