Datasheet

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
DS70318F-page 268 © 2008-2012 Microchip Technology Inc.
21.2 On-Chip Voltage Regulator
The dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 devices power their core digital
logic at a nominal 2.5V. This can create a conflict for
designs that are required to operate at a higher typical
voltage, such as 3.3V. To simplify system design, all
devices in the dsPIC33FJ06GS101/X02 and
dsPIC33FJ16GSX02/X04 families incorporate an on-chip
regulator that allows the device to run its core logic from
V
DD.
The regulator provides power to the core from the other
V
DD pins. When the regulator is enabled, a low-ESR
(less than 5 ohms) capacitor (such as tantalum or
ceramic) must be connected to the V
CAP pin
(Figure 21-1). This helps to maintain the stability of the
regulator. The recommended value for the filter
capacitor is provided in Table 24-13 located in
Section 24.1 “DC Characteristics”.
On a POR
, it takes approximately 20 μs for the on-chip
voltage regulator to generate an output voltage. During
this time, designated as T
STARTUP, code execution is
disabled. TSTARTUP is applied every time the device
resumes operation after any power-down.
FIGURE 21-1: CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR
(1,2,3)
21.3 BOR: Brown-Out Reset
The Brown-out Reset (BOR) module is based on an
internal voltage reference circuit. The main purpose of
the BOR module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (for
example, missing portions of the AC cycle waveform
due to bad power transmission lines, or voltage sags
due to excessive current draw when a large inductive
load is turned on).
A BOR generates a Reset pulse, which resets the
device. The BOR selects the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>).
If an oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the PWRT time-out (TPWRT) is applied
before the internal Reset is released. If TPWRT = 0 and
a crystal oscillator is being used, then a nominal delay
of TFSCM = 100 is applied. The total delay in this case
is TFSCM.
The BOR Status bit (RCON<1>) is set to indicate that a
BOR has occurred. The BOR circuit continues to
operate while in Sleep or Idle modes and resets the
device should V
DD fall below the BOR threshold
voltage.
Note: It is important for the low-ESR capacitor to
be placed as close as possible to the V
CAP
pin.
Note 1: These are typical operating voltages. Refer to
Table 24-13 located in Section 24.1 “DC
Characteristics” for the full operating
ranges of V
DD.
2: It is important for the low-ESR capacitor to
be placed as close as possible to the V
CAP
pin.
3: Typical VCAP pin voltage = 2.5V when
VDD ≥ VDDMIN.
VDD
VCAP
VSS
dsPIC33F
CEFC
3.3V
10 µF
Tantalum