Datasheet

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
DS70318F-page 262 © 2008-2012 Microchip Technology Inc.
20.3 Module Applications
This module provides a means for the SMPS dsPIC
DSC devices to monitor voltage and currents in a
power conversion application. The ability to detect
transient conditions and stimulate the dsPIC DSC
processor and/or peripherals, without requiring the
processor and ADC to constantly monitor voltages or
currents, frees the dsPIC DSC to perform other tasks.
The comparator module has a high-speed comparator
and an associated 10-bit DAC that provides a
programmable reference voltage to the inverting input
of the comparator. The polarity of the comparator out-
put is user-programmable. The output of the module
can be used in the following modes:
• Generate an Interrupt
• Trigger an ADC Sample and Convert Process
• Truncate the PWM Signal (current limit)
• Truncate the PWM Period (current minimum)
• Disable the PWM Outputs (Fault latch)
The output of the comparator module may be used in
multiple modes at the same time, such as: 1) generate
an interrupt, 2) have the ADC take a sample and con-
vert it, and 3) truncate the PWM output in response to
a voltage being detected beyond its expected value.
The comparator module can also be used to wake-up
the system from Sleep or Idle mode when the analog
input voltage exceeds the programmed threshold
voltage.
20.4 DAC
The range of the DAC is controlled through an analog
multiplexer that selects either AVDD/2, an internal ref-
erence source, INTREF, or an external reference
source, EXTREF. The full range of the DAC (AV
DD/2)
will typically be used when the chosen input source pin
is shared with the ADC. The reduced range option
(INTREF) will likely be used when monitoring current
levels using a current sense resistor. Usually, the
measured voltages in such applications are small
(<1.25V); therefore the option of using a reduced
reference range for the comparator extends the
available DAC resolution in these applications. The
use of an external reference enables the user to
connect to a reference that better suits their
application.
DACOUT, shown in Figure 20-1, can only be
associated with a single comparator at a given time.
20.5 Interaction with I/O Buffers
If the comparator module is enabled and a pin has
been selected as the source for the comparator, then
the chosen I/O pad must disable the digital input buffer
associated with the pad to prevent excessive currents
in the digital buffer due to analog input voltages.
20.6 Digital Logic
The CMPCONx register (see Register 20-1) provides
the control logic that configures the comparator
module. The digital logic provides a glitch filter for the
comparator output to mask transient signals in less
than two instruction cycles. In Sleep or Idle mode, the
glitch filter is bypassed to enable an asynchronous
path from the comparator to the interrupt controller.
This asynchronous path can be used to wake-up the
processor from Sleep or Idle mode.
The comparator can be disabled while in Idle mode if
the CMPSIDL bit is set. If a device has multiple
comparators, if any CMPSIDL bit is set, then the entire
group of comparators will be disabled while in Idle
mode. This behavior reduces complexity in the design
of the clock control logic for this module.
The digital logic also provides a one T
CY width pulse
generator for triggering the ADC and generating
interrupt requests.
The CMPDACx (see Register 20-2) register provides
the digital input value to the reference DAC.
If the module is disabled, the DAC and comparator are
disabled to reduce power consumption.
20.7 Comparator Input Range
The comparator has a limitation for the input Common
Mode Range (CMR) of (AV
DD – 1.5V), typical. This
means that both inputs should not exceed this range.
As long as one of the inputs is within the Common
Mode Range, the comparator output will be correct.
However, any input exceeding the CMR limitation will
cause the comparator input to be saturated.
If both inputs exceed the CMR, the comparator output
will be indeterminate.
20.8 DAC Output Range
The DAC has a limitation for the maximum reference
voltage input of (AVDD – 1.6) volts. An external
reference voltage input should not exceed this value or
the reference DAC output will become indeterminate.
20.9 Comparator Registers
The comparator module is controlled by the following
registers:
• CMPCONx: Comparator Control Register
• CMPDACx: Comparator DAC Control Register
Note: It should be ensured in software that
multiple DACOE bits are not set. The
output on the DACOUT pin will be indeter-
minate if multiple comparators enable the
DAC output.