Datasheet

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

(1)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

IRQEN6 PEND6 SWTRG6

TRGSRC6<4:0>

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-8 Unimplemented: Read as ‘0’

bit 7 IRQEN6: Interrupt Request Enable 6 bit

1 = Enable IRQ generation when requested conversion of channels AN13 and AN12 is completed

0 = IRQ is not generated

bit 6 PEND6: Pending Conversion Status 6 bit

1 = Conversion of channels AN13 and AN 12 is pending; set when selected trigger is asserted

0 = Conversion is complete

bit 5 SWTRG6: Software Trigger 6 bit

1 = Start conversion of AN13 (INTREF) and AN12 (EXTREF) (if selected by TRGSRC bits)

(2)

This bit is automatically cleared by hardware when the PEND6 bit is set.

0 = Conversion is not started

Note 1: This register is only implemented on the dsPIC33FJ16GS502 and dsPIC33FJ16GS504 devices.

2: The trigger source must be set as global software trigger prior to setting this bit to ‘1’. If other conversions

are in progress, conversion will be performed when the conversion resources are available.