Datasheet

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADBASE<15:8>

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0

ADBASE<7:1>

—

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-1 ADBASE<15:1>: This register contains the base address of the user’s ADC Interrupt Service Routine

jump table. This register, when read, contains the sum of the ADBASE register contents and the

encoded value of the PxRDY status bits.

The encoder logic provides the bit number of the highest priority PxRDY bits where P0RDY is the

highest priority, and P6RDY is the lowest priority.

bit 0 Unimplemented: Read as ‘0’

Note 1: The encoding results are shifted left two bits so bits 1-0 of the result are always zero.

2: As an alternative to using the ADBASE Register, the ADCP0-6 ADC Pair Conversion Complete Interrupts

can be used to invoke A to D conversion completion routines for individual ADC input pairs.

U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

— — — — PCFG11 PCFG10 PCFG9 PCFG8

bit 15 bit 8

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-12 Unimplemented: Read as ‘0’

bit 11-0 PCFG11:PCFG0: Analog-to-Digital Port Configuration Control bits

(1)

1 = Port pin in Digital mode, port read input enabled, Analog-to-Digital input multiplexor connected to

0 = Port pin in Analog mode, port read input disabled, Analog-to-Digital samples pin voltage

Note 1: Not all PCFGx bits are available on all devices. See Figure 19-1 through Figure 19-6 for the available

analog pins (PCFGx = ANx, where x = 0-11).