Datasheet

© 2008-2012 Microchip Technology Inc. DS70318F-page 241
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
FIGURE 19-4: ADC BLOCK DIAGRAM FOR dsPIC33FJ16GS402/404 DEVICES WITH ONE SAR
Even Numbered Inputs with Dedicated
Shared Sample and Hold
Data
Format
SAR
Core
Ten
Registers
16-bit
Sample and Hold (S&H) Circuits
Bus Interface
AN0
AN2
AN1
AN5
AN6
AN7
AN3
AN4