Datasheet

© 2008-2012 Microchip Technology Inc. DS70318F-page 239
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
FIGURE 19-2: ADC BLOCK DIAGRAM FOR dsPIC33FJ06GS102 DEVICES WITH ONE SAR
Even Numbered Inputs with Dedicated
Shared Sample and Hold
Data
Format
SAR
Core
Eight
Registers
16-bit
Sample and Hold (S&H) Circuits
Bus Interface
AN0
AN2
AN1
AN4
AN5
AN3