Datasheet

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
DS70318F-page 238 © 2008-2012 Microchip Technology Inc.
FIGURE 19-1: ADC BLOCK DIAGRAM FOR dsPIC33FJ06GS101 DEVICES WITH ONE SAR
Even Numbered Inputs with Dedicated
Shared Sample and Hold
Data
Format
SAR
Core
Eight
Registers
16-bit
Sample and Hold (S&H) Circuits
Bus Interface
AN0
AN1
AN3
AN6
AN7
AN2