Datasheet

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
DS70318F-page 206 © 2008-2012 Microchip Technology Inc.
REGISTER 15-10: SPHASEx: PWMx SECONDARY PHASE SHIFT REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SPHASEx<15:8>
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SPHASEx<7:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 SPHASEx<15:0>: Secondary Phase Offset for PWMxL Output Pin bits
(used in Independent PWM mode only)
Note 1: If PWMCONx<ITB> = 0, the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (IOCONx<PMOD> = 00, 01, or 10) SPHA-
SEx<15:0> = Not used
• True Independent Output mode (IOCONx<PMOD> = 11) PHASEx<15:0> = Phase shift value for
PWMxL only
2: If PWMCONx<ITB> = 1, the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (IOCONx<PMOD> = 00, 01, or 10) SPHA-
SEx<15:0> = Not used
• True Independent Output mode (IOCONx<PMOD> = 11) PHASEx<15:0> = Independent time base
period value for PWMxL only