Datasheet

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
DS70318F-page 202 © 2008-2012 Microchip Technology Inc.
REGISTER 15-6: PWMCONx: PWMx CONTROL REGISTER
HS/HC-0 HS/HC-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
FLTSTAT
(1)
CLSTAT
(1)
TRGSTAT FLTIEN CLIEN TRGIEN ITB
(3)
MDCS
(3)
bit 15 bit 8
R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
DTC<1:0>
— — —CAM
(2,3)
XPRES
(4)
IUE
bit 7 bit 0
Legend: HC = Hardware Clearable bit HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 FLTSTAT: Fault Interrupt Status bit
(1)
1 = Fault interrupt is pending
0 = No Fault interrupt is pending. This bit is cleared by setting FLTIEN = 0.
bit 14 CLSTAT: Current-Limit Interrupt Status bit
(1)
1 = Current-limit interrupt is pending
0 = No current-limit interrupt is pending. This bit is cleared by setting CLIEN = 0.
bit 13 TRGSTAT: Trigger Interrupt Status bit
1 = Trigger interrupt is pending
0 = No trigger interrupt is pending. This bit is cleared by setting TRGIEN = 0.
bit 12 FLTIEN: Fault Interrupt Enable bit
1 = Fault interrupt is enabled
0 = Fault interrupt is disabled and the FLTSTAT bit is cleared
bit 11 CLIEN: Current-Limit Interrupt Enable bit
1 = Current-limit interrupt enabled
0 = Current-limit interrupt disabled and the CLSTAT bit is cleared
bit 10 TRGIEN: Trigger Interrupt Enable bit
1 = A trigger event generates an interrupt request
0 = Trigger event interrupts are disabled and the TRGSTAT bit is cleared
bit 9 ITB: Independent Time Base Mode bit
(3)
1 = PHASEx/SPHASEx register provides time base period for this PWM generator
0 = PTPER register provides timing for this PWM generator
bit 8 MDCS: Master Duty Cycle Register Select bit
(3)
1 = MDC register provides duty cycle information for this PWM generator
0 = PDCx/SDCx register provides duty cycle information for this PWM generator
bit 7-6 DTC<1:0>: Dead-Time Control bits
11 = Reserved
10 = Dead-time function is disabled
01 = Negative dead time actively applied for all output modes
00 = Positive dead time actively applied for all output modes
bit 5-3 Unimplemented: Read as ‘0’
Note 1: Software must clear the interrupt status here and the corresponding IFS bit in the interrupt controller.
2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
3: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
4: To operate in External Period Reset mode, configure FCLCONx<CLMOD> = 0 and PWMCONx<ITB> = 1.