Datasheet

© 2008-2012 Microchip Technology Inc. DS70318F-page 197
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
FIGURE 15-1: SIMPLIFIED CONCEPTUAL BLOCK DIAGRAM OF HIGH-SPEED PWM
MUX
Latch
Comparator
Timer
PDC2
Phase
MUX
Latch
Comparator
Timer
PDC3
Phase
MUX
Latch
Comparator
Timer
PDC4
Phase
MUX
Latch
Comparator
Timer
PDC1
PWMCONx
LEBCONx
Channel 1
Dead-Time Generator
PTCON
SEVTCMP
Comparator
Special Event
IOCONx
PWM Enable and Mode Control
Channel 3
Dead-Time Generator
Channel 4
Dead-Time Generator
ALTDTRx, DTRx
Dead-Time Control
Special Event
Postscaler
FLTX
(1)
PWM3L
PWM3H
PWM2L
PWM2H
16-bit Data Bus
PWM1L
PWM1H
FCLCONx
Pin and Mode Control
MDC
ADC Trigger Control
Master Duty Cycle Register
Fault Mode and Pin Control
Pin Override Control
Special Event
PTPER
Timer Period
PWM GEN 1
PWM GEN 2
PWM GEN 4
PTMR
Master Time Base
Phase
PWM GEN 3
Channel 2
Dead-Time Generator
PWM4L
(1)
PWM4H
(1)
PWM User, Current-Limit and Fault Override and Routing Logic
Fault CLMT Override Logic
Trigger
Comparison Value
Fault Control
Logic
TRGCONx
Control for Blanking External Input Signals
SYNCO
(1)
SYNCIX
(1)
Note 1: These pins are remappable.
External Time Base
Synchronization