Datasheet

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04
DS70318F-page 18 © 2008-2012 Microchip Technology Inc.
CMP1A
CMP1B
CMP1C
CMP1D
CMP2A
CMP2B
CMP2C
CMP2D
CMP3A
CMP3B
CMP3C
CMP3D
CMP4A
CMP4B
CMP4C
CMP4D
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Comparator 1 Channel A
Comparator 1 Channel B
Comparator 1 Channel C
Comparator 1 Channel D
Comparator 2 Channel A
Comparator 2 Channel B
Comparator 2 Channel C
Comparator 2 Channel D
Comparator 3 Channel A
Comparator 3 Channel B
Comparator 3 Channel C
Comparator 3 Channel D
Comparator 4 Channel A
Comparator 4 Channel B
Comparator 4 Channel C
Comparator 4 Channel D
DACOUT O — No DAC output voltage
ACMP1-ACMP4 O — Yes DAC trigger to PWM module
EXTREF I Analog No External voltage reference input for the reference DACs
REFCLKO O — Yes REFCLKO output signal is a postscaled derivative of the system
clock
FLT1-FLT8
SYNCI1-SYNCI2
SYNCO1
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
PWM4L
PWM4H
I
I
O
O
O
O
O
O
O
O
O
ST
ST
—
—
—
—
—
—
—
—
—
Yes
Yes
Yes
No
No
No
No
No
No
Yes
Yes
Fault Inputs to PWM module
External synchronization signal to PWM Master Time Base
PWM master time base for external device synchronization
PWM1 low output
PWM1 high output
PWM2 low output
PWM2 high output
PWM3 low output
PWM3 high output
PWM4 low output
PWM4 high output
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
I
I/O
I
I/O
I
ST
ST
ST
ST
ST
ST
No
No
No
No
No
No
Data I/O pin for programming/debugging communication Channel 1
Clock input pin for programming/debugging communication
Channel 1
Data I/O pin for programming/debugging communication Channel 2
Clock input pin for programming/debugging communication
Channel 2
Data I/O pin for programming/debugging communication Channel 3
Clock input pin for programming/debugging communication
Channel 3
MCLR
I/P ST No Master Clear (Reset) input. This pin is an active-low Reset to the
device.
AV
DD P P No Positive supply for analog modules. This pin must be connected at
all times. AV
DD is connected to VDD.
AV
SS P P No Ground reference for analog modules. AVSS is connected to VSS.
V
DD P — No Positive supply for peripheral logic and I/O pins.
V
CAP P — No CPU logic filter capacitor connection.
V
SS P — No Ground reference for logic and I/O pins.
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin
Type
Buffer
Type
PPS
Capable
Description
Legend: CMOS = CMOS compatible input or output Analog = Analog input I = Input
ST = Schmitt Trigger input with CMOS levels P = Power O = Output
TTL = Transistor-Transistor Logic PPS = Peripheral Pin Select