Datasheet

dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04

8.2 Auxiliary Clock Generation

The auxiliary clock generation is used for a peripherals

that need to operate at a frequency unrelated to the

system clock such as a PWM or ADC.

The primary oscillator and internal FRC oscillator

sources can be used with an auxiliary PLL to obtain the

auxiliary clock. The auxiliary PLL has a fixed 16x

multiplication factor.

The auxiliary clock has the following configuration

restrictions:

• For proper PWM operation, auxiliary clock genera-

tion must be configured for 120 MHz (see parameter

OS56 in Table 24-18 in Section 24.0 “Electrical

Characteristics”). If a slower frequency is desired,

the PWM Input Clock Prescaler (Divider) Select bits

(PCLKDIV<2:0>) should be used.

• To achieve 1.04 ns PWM resolution, the auxiliary

clock must use the 16x auxiliary PLL (APLL). All

other clock sources will have a minimum PWM

resolution of 8 ns.

• If the primary PLL is used as a source for the aux-

iliary clock, the primary PLL should be configured

up to a maximum operation of 30 MIPS or less

8.3 Reference Clock Generation

The reference clock output logic provides the user with

the ability to output a clock signal based on the system

clock or the crystal oscillator on a device pin. The user

application can specify a wide range of clock scaling

prior to outputting the reference clock.