dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 16-bit Digital Signal Controllers (up to 16 KB Flash and up to 2 KB SRAM) with High-Speed PWM, ADC, and Comparators Operating Conditions Advanced Analog Features (Continued) • 3.0V to 3.6V, -40ºC to +150ºC, DC to 20 MIPS • 3.0V to 3.6V, -40ºC to +125ºC, DC to 40 MIPS • 3.0V to 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PRODUCT FAMILIES The device names, pin counts, memory sizes and peripheral availability of each device are listed below. The following pages show their pinout diagrams.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams = Pins are up to 5V tolerant 18-Pin SOIC 1 2 AN1/RA1 3 AN2/RA2 4 AN3/RP0(1)/CN0/RB0 5 OSC1/CLKI/AN6/RP1(1)/CN1/RB1 6 OSC2/CLKO/AN7/RP2(1)/CN2/RB2 TCK/PGED2/INT0/RP3(1)/CN3/RB3 7 8 TMS/PGEC2/RP4(1)/CN4/RB4 9 dsPIC33FJ06GS101 MCLR AN0/RA0 18 VDD 17 VSS 16 PWM1L/RA3 15 PWM1H/RA4 14 VCAP 13 VSS PGEC1/SDA1/RP7(1)/CN7/RB7 12 11 10 dsPIC33FJ06GS102 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 28-Pin SPDIP, SOIC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 dsPIC33FJ16GS402 MCLR AN0/RA0 AN1/RA1 AN2/RA2 AN3/RP0(1)/CN0/RB0 AN4/RP9(1)/CN9/RB9 AN5/RP10(1)/CN10/RB10 VSS OSC1/CLKIN/AN6/RP1(1)/CN1/RB1 OSC2/CLKO/AN7/RP2(1)/CN2/RB2 PGED2/INT0/RP3(1)/CN3/RB3 PGEC2/RP4(1)/CN4/RB4 VDD PGED3/RP8(1)/CN8/RB8 = Pins are up to 5V tolerant 28 27 26 25 24 23 22 21 20 19 18 17 16 15 = Pins are up to 5V tolerant 28-Pin SPDIP, SOIC Note 1: DS70318F-pa
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 28-Pin QFN-S(2) 28 27 26 25 24 23 22 1 21 2 20 3 19 4 dsPIC33FJ06GS102 18 5 17 6 16 7 15 8 9 10 11 12 13 14 = Pins are up to 5V tolerant PWM2L/RP14(1)/CN14/RB14 PWM2H/RP13(1)/CN13/RB13 TCK/RP12(1)/CN12/RB12 TMS/RP11(1)/CN11/RB11 VCAP VSS PGEC1/SDA/RP7(1)/CN7/RB7 28-Pin QFN-S(2) 28 27 26 25 24 23 22 1 21 2 20 3 19 4 dsPIC33FJ06GS202 18 5 17 6 16 7 15 8 9 10 11 12 13 14 = Pins are up to 5V tolerant PWM2L/RP14(1)/CN14/RB14 PWM2H/RP13(1)/CN13/RB13 TCK/RP12(1
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 28-Pin QFN-S(2) 28 27 26 25 24 23 22 1 21 2 20 3 19 4 dsPIC33FJ16GS402 18 5 17 6 16 7 15 8 9 10 11 12 13 14 = Pins are up to 5V tolerant PWM2L/RP14(1)/CN14/RB14 PWM2H/RP13(1)/CN13/RB13 TCK/PWM3L/RP12(1)/CN12/RB12 TMS/PWM3H/RP11(1)/CN11/RB11 VCAP VSS PGEC1/SDA/RP7(1)/CN7/RB7 28-Pin QFN-S(2) 28 27 26 25 24 23 22 1 21 2 20 3 19 4 dsPIC33FJ16GS502 18 5 17 6 16 7 15 8 9 10 11 12 13 14 = Pins are up to 5V tolerant PWM2L/RP14(1)/CN14/RB14 PWM2H/RP13(1)/CN13/RB1
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 44-Pin VTLA(2) PGED2/INT0/RP3(1)/CN3/RB3 PGEC2/RP4(1)/CN4/RB4 RP18(1)/CN18/RC2 RP23(1)/CN23/RC7 RP24(1)/CN24/RC8 VSS VDD PGED3/RP8(1)/CN8/RB8 PGEC3/RP15(1)/CN15/RB15 TDO/RP5(1)/CN5/RB5 PGED1/TDI/SCL/RP6(1)/CN6/RB6 = Pins are up to 5V tolerant 44 43 42 41 40 39 38 37 36 35 34 33 OSC2/CLKO/AN7/RP2(1)/CN2/RB2 1 32 OSC1/CLKI/AN6/RP1(1)/CN1/RB1 RP20(1)/CN20/RC4 2 31 RP17(1)/CN17/RC1 RP21(1)/CN21/RC5 3 30 VSS RP22(1)/
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 44-Pin VTLA(2) PGED2/DACOUT/INT0/RP3(1)/CN3/RB3 PGEC2/RP4(1)/CN4/RB4 AN9/EXTREF/CMP4D/RP18(1)/CN18/RC2 RP23(1)/CN23/RC7 VSS RP24(1)/CN24/RC8 VDD PGED3/RP8(1)/CN8/RB8 PGEC3/RP15(1)/CN15/RB15 TDO/RP5(1)/CN5/RB5 PGED1/TDI/SCL/RP6(1)/CN6/RB6 = Pins are up to 5V tolerant 44 43 42 41 40 39 38 37 36 35 34 33 OSC2/CLKO/AN7/CMP3D/CMP4B/RP2(1)/CN2/RB2 PGEC1/SDA/RP7 /CN7/RB7 1 32 OSC1/CLKI/AN6/CMP3C/CMP4A/RP1(1)/CN1/RB1 RP20(1)/C
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 44-Pin QFN(2) PGED2/INT0/RP3(1)/CN3/RB3 RP18(1)/CN18/RC2 PGEC2/RP4(1)/CN4/RB4 RP23(1)/CN23/RC7 VDD VSS RP24(1)/CN24/RC8 PGED3/RP8(1)/CN8/RB8 PGEC3/RP15(1)/CN15/RB15 PGED1/TDI/SCL/RP6(1)/CN6/RB6 TDO/RP5(1)/CN5/RB5 = Pins are up to 5V tolerant 44 43 42 41 40 39 38 37 36 35 34 PGEC1/SDA/RP7(1)/CN7/RB7 RP20(1)/CN20/RC4 RP21(1)/CN21/RC5 RP22(1)/CN22/RC6 OSC2/CLKO/AN7/RP2(1)/CN2/RB2 OSC1/CLKI/AN6/RP1(1)/CN1/RB1 1 33 2 3 32 31 RP
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 44-Pin QFN(2) PGED2/DACOUT/INT0/RP3(1)/CN3/RB3 AN9/EXTREF/CMP4D/RP18(1)/CN18/RC2 PGEC2/RP4(1)/CN4/RB4 RP23(1)/CN23/RC7 VDD VSS RP24(1)/CN24/RC8 PGED3/RP8(1)/CN8/RB8 PGEC3/RP15(1)/CN15/RB15 PGED1/TDI/SCL/RP6(1)/CN6/RB6 TDO/RP5(1)/CN5/RB5 = Pins are up to 5V tolerant 44 43 42 41 40 39 38 37 36 35 34 PGEC1/SDA/RP7(1)/CN7/RB7 RP20(1)/CN20/RC4 RP21(1)/CN21/RC5 RP22(1)/RN22/RC6 RP19(1)/CN19/RC3 VSS VCAP 1 2 3 4 5 6 33 32 31 30 29 28
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 44-Pin TQFP VDD VSS RP24(1)/CN24/RC8 RP23(1)/CN23/RC7 RP18(1)/CN18/RC2 PGEC2/RP4(1)/CN4/RB4 PGED2/INT0/RP3(1)/CN3/RB3 40 39 38 37 36 35 34 42 41 PGED1/TDI/SCL/RP6(1)/CN6/RB6 TDO/RP5(1)/CN5/RB5 PGEC3/RP15(1)/CN15/RB15 PGED3/RP8(1)/CN8/RB8 43 44 VDD RP26(1)/CN26/RC10 RP25(1)/CN25/RC9 AN5/RP10(1)/CN10/RB10 AN4/RP9(1)/CN9/RB9 AN3/RP0(1)/CN0/RB0 AN2/RA2 RP28 /CN28/RC12 AN0/RA0 AN1/RA1 25 24 23 OSC2/CLKO/AN7/RP2(1)/CN2/RB2 OSC1/C
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Pin Diagrams (Continued) 44-Pin TQFP VDD VSS RP24(1)/CN24/RC8 RP23(1)/CN23/RC7 AN9/EXTREF/CMP4D/RP18(1)/CN18/RC2 PGEC2/RP4(1)/CN4/RB4 PGED2/DACOUT/INT0/RP3(1)/CN3/RB3 40 39 38 37 36 35 34 42 41 43 PGED1/TDI/SCL/RP6(1)/CN6/RB6 TDO/RP5(1)/CN5/RB5 PGEC3/RP15(1)/CN15/RB15 PGED3/RP8(1)/CN8/RB8 44 VDD AN10/RP26(1)/CN26/RC10 AN11/RP25(1)/CN25/RC9 AN5/CMP2D/CMP3B/RP10(1)/CN10/RB10 AN4/CMP2C/CMP3A/RP9(1)/CN9/RB9 AN3/CMP1D/CMP2B/RP0(1)/CN0/RB0 AN2/CMP1C/CMP2A/R
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Table of Contents dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Product Families .......................................................................................... 2 1.0 Device Overview ........................................................................................................................................................................ 15 2.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers ..........................
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Referenced Sources This device data sheet is based on the following individual chapters of the “dsPIC33F/PIC24H Family Reference Manual”. These documents should be considered as the primary reference for the operation of a particular module or device feature. Note: To access the documents listed below, browse to the documentation section of the dsPIC33FJ16GS504 product page of the Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 1.0 DEVICE OVERVIEW Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest “dsPIC33F/PIC24H Family Reference Manual” sections.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 1-1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 BLOCK DIAGRAM PSV & Table Data Access Control Block Y Data Bus X Data Bus Interrupt Controller PORTA 16 8 16 16 16 Data Latch Data Latch X RAM Y RAM Address Latch Address Latch 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic PORTB 16 23 16 16 PORTC Address Generator Units Address Latch Program Memory EA MUX Data Latch Pins ROM Latch 24 Instruction Reg
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 1-1: Pin Name PINOUT I/O DESCRIPTIONS Pin Type Buffer Type PPS Capable Description AN0-AN11 I Analog No Analog input channels CLKI I ST/CMOS No CLKO O — No External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type Buffer Type PPS Capable CMP1A CMP1B CMP1C CMP1D CMP2A CMP2B CMP2C CMP2D CMP3A CMP3B CMP3C CMP3D CMP4A CMP4B CMP4C CMP4D I I I I I I I I I I I I I I I I Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog No No No No No No No No No No No No No No No No DACOUT O — No DAC output voltage ACMP1-ACMP4 O — Yes DAC trigger to PWM module E
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT DIGITAL SIGNAL CONTROLLERS Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the dsPIC33F/PIC24H Family Reference Manual, which is available from the Microchip website (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 0.1 µF Ceramic 10 µF Tantalum R R1 VSS VDD 2.4 VCAP VDD dsPIC33F VSS VDD VSS VDD AVSS VDD AVDD VSS 0.1 µF Ceramic 0.1 µF Ceramic 0.1 µF Ceramic L1(1) 1: As an option, instead of a hard-wired connection, an inductor (L1) can be substituted between VDD and AVDD to improve ADC noise rejection. The inductor impedance should be less than 1Ω and the inductor capacity greater than 10 mA.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 2.5 ICSP™ Pins FIGURE 2-3: The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 2.8 Configuration of Analog and Digital Pins During ICSP Operations If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as “digital” pins, by setting all bits in the ADPCFG register.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 2-4: DIGITAL PFC IPFC VHV_BUS |VAC| k1 k3 VAC k2 ADC Channel FET Driver ADC Channel PWM Output ADC Channel dsPIC33FJ06GS101 FIGURE 2-5: BOOST CONVERTER IMPLEMENTATION IPFC VINPUT VOUTPUT k1 k3 ADC Channel k2 FET Driver ADC Channel PWM Output ADC Channel dsPIC33FJ06GS101 © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 2-6: SINGLE-PHASE SYNCHRONOUS BUCK CONVERTER 12V Input 5V Output I5V FET Driver k1 PWM PWM k7 ADC Channel Analog Comp. k2 ADC Channel dsPIC33FJ06GS202 FIGURE 2-7: MULTI-PHASE SYNCHRONOUS BUCK CONVERTER 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 2-8: OFF-LINE UPS VDC Push-Pull Converter Full-Bridge Inverter VOUT+ VBAT + VOUTGND GND FET Driver FET Driver PWM PWM k2 k1 ADC ADC or Analog Comp. k3 FET Driver FET Driver FET Driver FET Driver PWM PWM PWM PWM dsPIC33FJ16GS504 ADC k4 k5 ADC ADC ADC PWM FET Driver k6 + Battery Charger © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 2-9: INTERLEAVED PFC VOUT+ |VAC| k4 VAC k3 k1 k2 VOUTFET Driver ADC Channel ADC Channel DS70318F-page 26 PWM FET Driver ADC Channel PWM ADC Channel ADC Channel dsPIC33FJ06GS202 © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 2-10: PHASE-SHIFTED FULL-BRIDGE CONVERTER VIN+ Gate 6 Gate 3 Gate 1 VOUT+ S1 S3 VOUT- Gate 2 Gate 4 Gate 5 Gate 6 Gate 5 VIN- FET Driver k2 PWM ADC Channel k1 Analog Ground Gate 1 S1 FET Driver PWM Gate 3 S3 FET Driver ADC Channel dsPIC33FJ06GS202 PWM Gate 2 Gate 4 © 2008-2012 Microchip Technology Inc.
AC-TO-DC POWER SUPPLY WITH PFC AND THREE OUTPUTS (12V, 5V, AND 3.3V) ZVT with Current Doubler Synchronous Rectifier VHV_BUS Isolation Barrier VOUT IZVT 3.3V Multi-Phase Buck Stage 3.3V Output 12V Input I3.3V_1 FET Driver FET Driver k4 FET Driver 5V Output 5V Buck Stage I3.3V_2 ADC ADC Channel Channel FET Driver ADC Ch. ADC Ch. PWM Output PWM ADC Ch. k5 FET Driver k6 k7 ADC Channel Analog Comp.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 3.0 CPU Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. “CPU” (DS70204) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 3.3 Special MCU Features The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices support 16/16 and 32/16 divide operations, both fractional and integer. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 3-2: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PROGRAMMER’S MODEL D15 D0 W0/WREG PUSH.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 3-1: SR: CPU STATUS REGISTER (CONTINUED) bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits(2) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU I
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 3-2: U-0 — bit 15 U-0 — R/W-0 SATB Legend: R = Readable bit 0’ = Bit is cleared bit 11 bit 10-8 U-0 — R/W-0 US R/W-0 EDT(1) R-0 R-0 DL<2:0> R-0 bit 8 R/W-0 SATA bit 7 bit 15-13 bit 12 CORCON: CORE CONTROL REGISTER R/W-1 SATDW R/W-0 ACCSAT C = Clearable bit W = Writable bit ‘x = Bit is unknown R/C-0 IPL3(2) R/W-0 PSV R/W-0 RND R/W-0 IF bit 0 -n = Value at POR ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ Unimplemented: Read a
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 3.5 Arithmetic Logic Unit (ALU) 3.6 DSP Engine The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU can affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 3-3: DSP ENGINE BLOCK DIAGRAM 40 S a 40 Round t 16 u Logic r a t e 40-bit Accumulator A 40-bit Accumulator B Carry/Borrow Out Saturate Carry/Borrow In Adder Negate 40 40 40 16 X Data Bus Barrel Shifter 40 Y Data Bus Sign-Extend 32 16 Zero Backfill 32 33 17-bit Multiplier/Scaler 16 16 To/From W Array DS70318F-page 36 © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 3.6.1 MULTIPLIER The 17-bit x 17-bit multiplier is capable of signed or unsigned operation and can multiplex its output using a scaler to support either 1.31 fractional (Q31) or 32-bit integer results. Unsigned operands are zero-extended into the 17th bit of the multiplier input value. Signed operands are sign-extended into the 17th bit of the multiplier input value.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 The SA and SB bits are modified each time data passes through the adder/subtracter, but can only be cleared by the user application. When set, they indicate that the accumulator has overflowed its maximum range (bit 31 for 32-bit saturation or bit 39 for 40-bit saturation) and will be saturated (if saturation is enabled). When saturation is not enabled, SA and SB default to bit 39 overflow and thus, indicate that a catastrophic overflow has occurred.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 3.6.3.2 Data Space Write Saturation 3.6.4 BARREL SHIFTER In addition to adder/subtracter saturation, writes to data space can also be saturated, but without affecting the contents of the source accumulator. The data space write saturation logic block accepts a 16-bit, 1.15 fractional value from the round logic block as its input, together with overflow status from the original source (accumulator) and the 16-bit round adder.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318F-page 40 © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.0 Note: MEMORY ORGANIZATION This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 4. “Program Memory” (DS70202) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.2 All dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.2 Data Address Space The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 CPU has a separate, 16-bitwide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps is shown in Figure 4-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This arrangement gives a data space address range of 64 Kbytes or 32K words.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 4-3: DATA MEMORY MAP FOR dsPIC33FJ06GS101/102 DEVICES WITH 256 BYTES OF RAM MSB Address MSb 2-Kbyte SFR Space 256 bytes SRAM Space LSb 0x0000 0x0001 SFR Space 0x07FF 0x0801 0x087F 0x0881 0x07FE 0x0800 X Data RAM (X) Y Data RAM (Y) 0x087E 0x0880 0x08FF 0x0901 0x08FE 0x0900 0x1FFF 0x2001 0x1FFE 0x8001 0x8000 8-Kbyte Near Data Space 0x2000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF DS70318F-page 44 LSB Address
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 4-4: DATA MEMORY MAP FOR dsPIC33FJ06GS202 DEVICE WITH 1 KB RAM MSB Address MSb 2-Kbyte SFR Space 1-Kbyte SRAM Space LSB Address 16 bits LSb 0x0000 0x0001 SFR Space 0x07FF 0x0801 0x09FF 0x0A01 0x07FE 0x0800 X Data RAM (X) Y Data RAM (Y) 0x09FE 0x0A00 0x0BFF 0x0C01 0x0BFE 0x0C00 0x1FFF 0x2001 0x1FFE 0x8001 0x8000 8-Kbyte Near Data Space 0x2000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF © 2008-2012 Microchip Te
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 4-5: DATA MEMORY MAP FOR dsPIC33FJ16GS402/404/502/504 DEVICES WITH 2 KB RAM MSB Address MSb 2-Kbyte SFR Space 2-Kbyte SRAM Space LSb 0x0000 0x0001 SFR Space 0x07FF 0x0801 0x0BFF 0x0C01 0x07FE 0x0800 X Data RAM (X) Y Data RAM (Y) 0x0BFE 0x0C00 0x0FFF 0x1001 0x0FFE 0x1000 0x1FFF 0x2001 0x1FFE 0x8001 0x8000 8-Kbyte Near Data Space 0x2000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF DS70318F-page 46 LSB Address 16
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.2.5 X AND Y DATA SPACES The core has two data spaces, X and Y. These data spaces can be considered either separate (for some DSP instructions), or as one unified linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths.
SFR Name SFR Addr CPU CORE REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets WREG0 0000 Working Register 0 0000 WREG1 0002 Working Register 1 0000 WREG2 0004 Working Register 2 0000 WREG3 0006 Working Register 3 0000 WREG4 0008 Working Register 4 0000 WREG5 000A Working Register 5 0000 WREG6 000C Working Register 6 0000 WREG7 000E Working Register 7 0000 WREG8 0010 Working Registe
SFR Name CPU CORE REGISTER MAP (CONTINUED) SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets XMODSRT 0048 XS<15:1> 0 xxxx XMODEND 004A XE<15:1> 1 xxxx YMODSRT 004C YS<15:1> 0 xxxx YMODEND 004E YE<15:1> 1 xxxx XBREV 0050 BREN DISICNT 0052 — Legend: XB<14:0> — xxxx Disable Interrupts Counter Register xxxx x = unknown value on Reset, — = unimplemented, read as ‘0’.
File Name INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06GS101 DEVICES ONLY SFR Addr.
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06GS102 DEVICES ONLY File Name SFR Addr.
File Name INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ06G202 DEVICES ONLY SFR Addr. Bit 15 Bit 14 Bit 13 INTCON1 0080 NSTDIS OVAERR OVBERR INTCON2 0082 ALTIVT DISI — — — IFS0 0084 — — ADIF U1TXIF IFS1 0086 — — INT2IF IFS3 008A — — — IFS4 008C — — IFS5 008E PWM2IF © 2008-2012 Microchip Technology Inc.
INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ16GS402/404 DEVICES ONLY DS70318F-page 53 File Name SFR Addr.
File Name INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ16GS502 DEVICES ONLY © 2008-2012 Microchip Technology Inc. SFR Addr.
File Name INTERRUPT CONTROLLER REGISTER MAP FOR dsPIC33FJ16GS504 DEVICES ONLY SFR Addr.
SFR Name TMR1 SFR Addr TIMER REGISTER MAP FOR dsPIC33FJ06GS101 AND dsPIC33FJ06GSX02 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0100 Timer1 Register 0000 PR1 0102 Period Register 1 FFFF T1CON 0104 TMR2 0106 Timer2 Register PR2 010C Period Register 2 TON — TSIDL TSIDL — — — — — — — — — — — — T2CON 0110 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’.
SFR Name SFR Addr INPUT CAPTURE REGISTER MAP FOR dsPIC33FJ16GSX02 AND dsPIC33FJ16GSX04 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 — — ICSIDL — — — — Bit 8 Bit 7 IC1BUF 0140 IC1CON 0142 IC2BUF 0144 IC2CON 0146 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
HIGH-SPEED PWM GENERATOR 1 REGISTER MAP File Name Addr Offset Bit 15 PWMCON1 0420 FLTSTAT IOCON1 0422 PENH FCLCON1 0424 IFLTMOD PDC1 0426 PDC1<15:0> PHASE1 0428 PHASE1<15:0> DTR1 042A — — — — Bit 14 Bit 13 CLSTAT TRGSTAT PENL POLH Bit 12 Bit 11 Bit 10 FLTIEN CLIEN TRGIEN POLL PMOD<1:0> CLSRC<4:0> Bit 9 Bit 8 Bit 7 Bit 6 ITB MDCS DTC<1:0> OVRENH OVRENL OVRDAT<1:0> CLPOL CLMOD Bit 5 Bit 4 — — FLTDAT<1:0> All Resets XPRES IUE 0000 SWAP OSYNC 0000 Bi
HIGH-SPEED PWM GENERATOR 3 REGISTER MAP FOR dsPIC33FJ16GSX02/X04 DEVICES ONLY File Name Addr Offset Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 PWMCON3 0460 FLTSTAT CLSTAT TRGSTAT FLTIEN CLIEN TRGIEN IOCON3 0462 PENH PENL POLH POLL FCLCON3 0464 IFLTMOD PDC3 0466 PDC3<15:0> PHASE3 0468 PHASE3<15:0> DTR3 046C — — — — PMOD<1:0> CLSRC<4:0> Bit 9 Bit 8 Bit 7 Bit 6 ITB MDCS DTC<1:0> OVRENH OVRENL OVRDAT<1:0> CLPOL CLMOD Bit 5 Bit 4 — — FLTDAT<1:0> All Resets
I2C1 REGISTER MAP SFR Name SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets I2C1RCV 0200 — — — — — — — — Receive Register 0000 I2C1TRN 0202 — — — — — — — — Transmit Register 00FF I2C1BRG 0204 — — — — — — — I2C1CON 0206 I2CEN — IPMIEN A10M DISSLW SMEN GCEN STREN GCSTAT ADD10 IWCOL I2COV 0000 ACKDT ACKEN RCEN PEN RSEN SEN D_A P S R_W RBF TBF 1000 I2C1STAT 0
HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ06GS101 DEVICES ONLY SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 ADCON 0300 ADON — ADSIDL SLOWCLK — GSWTRG — FORM ADPCFG 0302 — — — — — — — — ADSTAT 0306 — — — — — — — ADBASE 0308 ADCPC0 030A IRQEN1 PEND1 SWTRG1 TRGSRC1<4:0> IRQEN0 PEND0 SWTRG0 ADCPC1 030C IRQEN3 PEND3 SWTRG3 TRGSRC3<4:0> — — — ADCBUF0 0320 ADC Data Buffer 0 xxxx ADCBUF1 0322 ADC Data Buffer 1 xxxx ADCBUF2 0
HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ06GS202 DEVICES ONLY SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 ADCON 0300 ADON — ADSIDL SLOWCLK — GSWTRG — FORM EIE ORDER ADPCFG 0302 — — — — — — — — — — PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 ADSTAT 0306 — — — — — — — — — P6RDY — — — P2RDY P1RDY P0RDY ADBASE 0308 SFR Name Bit 5 Bit 4 SEQSAMP ASYNCSAMP Bit 3 Bit 2 Bit 1 — ADCS<2:0> ADBASE<15:1> All Resets 0003
HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ16GS502 DEVICES ONLY SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 ADCON 0300 ADON — ADSIDL SLOWCLK — GSWTRG — ADPCFG 0302 — — — — — — — ADSTAT 0306 — — — — — — — ADBASE 0308 SFR Name Bit 7 Bit 6 Bit 5 Bit 4 FORM EIE ORDER — PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 — — P6RDY — — P3RDY P2RDY P1RDY P0RDY SEQSAMP ASYNCSAMP Bit 3 — Bit 2 Bit 1 Bit 0 ADCS<2:0> ADBASE<15:1>
HIGH-SPEED 10-BIT ADC REGISTER MAP FOR dsPIC33FJ16GS504 DEVICES ONLY SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 ADCON 0300 ADON — ADSIDL ADPCFG 0302 — — — ADSTAT 0306 — — — SFR Name Bit 11 Bit 10 SLOWCLK — GSWTRG — PCFG11 PCFG10 — — — Bit 9 Bit 8 — FORM PCFG9 PCFG8 — — Bit 7 Bit 6 Bit 5 Bit 4 SEQSAMP ASYNCSAMP Bit 3 — Bit 2 Bit 1 Bit 0 ADCS<2:0> All Resets EIE ORDER PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000 — P6RDY P5RDY P4RDY P3RDY P2RDY
File Name ANALOG COMPARATOR CONTROL REGISTER MAP FOR dsPIC33FJ06GS202 DEVICES ONLY ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 CMPCON1 0540 CMPON — CMPSIDL — — — — DACOE CMPDAC1 0542 — — — — — — CMPCON2 0544 CMPON — CMPSIDL — — — CMPDAC2 0546 — — — — — — TABLE 4-32: Bit 7 Bit 6 INSEL<1:0> Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EXTREF — CMPSTAT — CMPPOL RANGE CMREF<9:0> — DACOE INSEL<1:0> EXTREF — All Resets 0000 0000 CMPSTAT — C
PERIPHERAL PIN SELECT INPUT REGISTER MAP SFR Name SFR Addr Bit 15 Bit 14 RPINR0 0680 — — RPINR1 0682 — — RPINR2 0684 — — RPINR3 0686 — RPINR7 068E — RPINR11 0696 — — RPINR18 06A4 — — RPINR20 06A8 — — RPINR21 06AA — — RPINR29 06BA — — RPINR30 06BC — RPINR31 06BE — RPINR32 06C0 RPINR33 RPINR34 Legend: Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets — — — — — — — — 3F00 — — T1CKR<5:0> — — — — 0000 — T3CKR<5:0> — — T2CK
File Name PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ06GS102, dsPIC33FJ06GS202, dsPIC33FJ16GS402 AND dsPIC33FJ16GS502 Addr Bit 15 Bit 14 RPOR0 06D0 — — RPOR1 06D2 — — RPOR2 06D4 — RPOR3 06D6 — RPOR4 06D8 RPOR5 Bit 6 RP1R<5:0> — — RP0R<5:0> 0000 RP3R<5:0> — — RP2R<5:0> 0000 — RP5R<5:0> — — RP4R<5:0> 0000 — RP7R<5:0> — — RP6R<5:0> 0000 — — RP9R<5:0> — — RP8R<5:0> 0000 06DA — — RP11R<5:0> — — RP10R<5:0> 0000 RPOR6 06DC — — RP13R<5:0>
SFR Name PORTA REGISTER MAP SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets TRISA 02C0 — — — — — — — — — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 001F PORTA 02C2 — — — — — — — — — — — RA4 RA3 RA2 RA1 RA0 xxxx LATA 02C4 — — — — — — — — — — — LATA4 LATA3 LATA2 LATA1 LATA0 0000 ODCA 02C6 — — — — — — — — — — — ODCA4 ODCA3 — — — 0000 Legend: x =
SYSTEM CONTROL REGISTER MAP SFR Name SFR Addr Bit 15 Bit 14 IOPUWR RCON 0740 TRAPR OSCCON 0742 — Bit 13 Bit 12 Bit 11 Bit 10 — — — — COSC<2:0> — CLKDIV 0744 ROI PLLFBD 0746 — — — — REFOCON 074E ROON — ROSSLP ROSEL OSCTUN 0748 — — — — — 0750 ENAPLL APLLCK SELACLK — — ACLKCON Legend: Note 1: 2: Bit 8 CM VREGS NOSC<2:0> DOZEN FRCDIV<2:0> — — Bit 7 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR xxxx(1) CLKLOCK IOLOC
SFR Name PMD REGISTER MAP FOR dsPIC33FJ06GS202 DEVICES ONLY SFR Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 PMD1 0770 — — — T2MD T1MD — PMD2 0772 — — — — — — PMD3 0774 — — — — — CMPMD PMD4 0776 — — — — — — PMD6 077A — — — — — — PMD7 077C — — — — — — CMP2MD Legend: — — ADCMD 0000 — — OC1MD 0000 — — — — 0000 — REFOMD — — — 0000 — — — — — 0000 — — — — — 0000 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 Bit 4 PW
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.2.6 4.3 SOFTWARE STACK In addition to its use as a working register, the W15 register in the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It predecrements for stack pops and post-increments for stack pushes, as shown in Figure 4-6.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 4-48: FUNDAMENTAL ADDRESSING MODES SUPPORTED Addressing Mode Description File Register Direct The address of the file register is specified explicitly. Register Direct The contents of a register are accessed directly. Register Indirect The contents of Wn forms the Effective Address (EA). Register Indirect Post-Modified The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.4 Modulo Addressing Note: Modulo Addressing mode is a method used to provide an automated means to support circular data buffers using hardware. The objective is to remove the need for software to perform data address boundary checks when executing tightly looped code, as is typical in many DSP algorithms. Modulo Addressing can operate in either data or program space (since the data pointer mechanism is essentially the same for both).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.4.3 MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W register.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 4-8: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-Word Bit-Reversed Buffer TABLE 4-49: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY) Normal Address Bit-Reversed Address A3 A2 A1 A0 Decimal A3 A2 A1 A0 Decimal 0
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.6 Interfacing Program and Data Memory Spaces 4.6.1 The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 architecture uses a 24-bit-wide program space and a 16-bit-wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 4-9: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) Program Counter 0 0 23 bits EA Table Operations(2) 1/0 1/0 TBLPAG 8 bits 16 bits 24 bits Select Program Space Visibility(1) (Remapping) 0 EA 1 0 PSVPAG 8 bits 15 bits 23 bits User/Configuration Space Select Byte Select Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and d
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.6.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 4.6.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to stored constant data from the data space without the need to use special instructions (such as TBLRDL/H).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318F-page 80 © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 5.0 FLASH PROGRAM MEMORY power (VDD), ground (VSS) and Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 5.2 RTSP Operation The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one word at a time. Table 24-12 shows typical erase and programming times.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0(1) R/W-0(1) R/W-0(1) U-0 U-0 U-0 U-0 U-0 WR WREN WRERR — — — — — bit 15 bit 8 R/W-0(1) U-0 — U-0 ERASE — R/W-0(1) U-0 R/W-0(1) R/W-0(1) R/W-0(1) (2) — NVMOP<3:0> bit 7 bit 0 Legend: SO = Settable Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 WR: Wri
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 5-2: NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 NVMKEY<7:0>: Key Register bits (write-only) DS70318F-page 84 x = Bit is unkno
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 5.4.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. One row of program Flash memory can be programmed at a time. To achieve this, it is necessary to erase the 8-row erase page that contains the desired row. The general process is: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 EXAMPLE 5-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0,
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 6.0 RESETS A simplified block diagram of the Reset module is shown in Figure 6-1. Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. “Reset” (DS70192) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 RCON: RESET CONTROL REGISTER(1) REGISTER 6-1: R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 TRAPR IOPUWR — — — — CM VREGS bit 15 bit 8 R/W-0 EXTR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 TRAPR: Trap Reset Flag bit 1 =
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED) bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit 1 = A Power-up Reset has occurred 0 = A Power-up Reset has not occurred Note 1: 2: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not cause a device Reset.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 6.1 System Reset • Cold Reset • Warm Reset A warm Reset is the result of all the other Reset sources, including the RESET instruction. On warm Reset, the device will continue to operate from the current clock source as indicated by the Current Oscillator Selection (COSC<2:0>) bits in the Oscillator Control (OSCCON<14:12>) register. A cold Reset is the result of a Power-on Reset (POR) or a Brown-out Reset (BOR).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 6-2: SYSTEM RESET TIMING VBOR VPOR VDD TPOR 1 POR Reset TBOR 2 BOR Reset 3 TPWRT SYSRST 4 Oscillator Clock TOSCD TOST TLOCK 6 TFSCM FSCM 5 Reset Device Status Run Time Note 1: POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is active until VDD crosses the VPOR threshold and the delay, TPOR, has elapsed.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 6.2 Power-on Reset (POR) A Power-on Reset (POR) circuit ensures the device is reset from power-on. The POR circuit is active until VDD crosses the VPOR threshold and the delay, TPOR, has elapsed. The delay, TPOR, ensures the internal device bias circuits become stable. The device supply voltage characteristics must meet the specified starting voltage and rise rate requirements to generate the POR. Refer to Section 24.0 “Electrical Characteristics” for details.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 6.3 External Reset (EXTR) The external Reset is generated by driving the MCLR pin low. The MCLR pin is a Schmitt trigger input with an additional glitch filter. Reset pulses that are longer than the minimum pulse width will generate a Reset. Refer to Section 24.0 “Electrical Characteristics” for minimum pulse width specifications. The external Reset (MCLR) pin (EXTR) bit in the Reset Control (RCON) register is set to indicate the MCLR Reset. 6.3.0.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 6.8.2 UNINITIALIZED W REGISTER RESET The VFC occurs when the program counter is reloaded with an interrupt or trap vector. Any attempt to use the uninitialized W register as an Address Pointer will Reset the device. The W register array (with the exception of W15) is cleared during all Resets and is considered uninitialized until written to. 6.8.3 6.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 7.0 INTERRUPT CONTROLLER Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 41. “Interrupts (Part IV)” (DS70300) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Decreasing Natural Order Priority FIGURE 7-1: Note 1: DS70318F-page 96 dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 ~ ~ ~ Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 ~ ~ ~ Interrupt Vector 116 Interru
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 7-1: INTERRUPT VECTORS Vector Number Interrupt Request (IQR) 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22-23 24 25 26 27 28 29-36 37 38-64 65 66-72 73 74-101 102 103 104 105 106-110 111 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14-15 16 17 18 19 20 21-28 29 30-56 57 58-64 65 66-93 94 95 96 97 98-102 103 112 113 114-117 118 119 120 121 122 123 124 125 104 105 106-109 110 111 112 113 114 115 116 117 IVT Address AIVT Address Interrupt Source Highest Natural Or
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 7.3 Interrupt Control and Status Registers The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices implement 27 registers for the interrupt controller: • • • • • • INTCON1 INTCON2 IFSx IECx IPCx INTTREG 7.3.1 INTCON1 AND INTCON2 Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit as well as the control and status flags for the processor trap sources.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-1: SR: CPU STATUS REGISTER(1) R-0 R-0 R/C-0 R/C-0 R-0 R/C-0 R -0 R/W-0 OA OB SA SB OAB SAB DA DC bit 15 bit 8 R/W-0(3) R/W-0(3) R/W-0(3) IPL<2:0>(2) R-0 R/W-0 R/W-0 R/W-0 R/W-0 RA N OV Z C bit 7 bit 0 Legend: C = Clearable bit R = Readable bit U = Unimplemented bit, read as ‘0’ S = Settable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown IPL<2:0>: CPU Interrup
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NSTDIS OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 SFTACERR DIV0ERR — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is un
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-3: INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED) bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as ‘0’ © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use alternate vector
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — ADIF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED) bit 1 IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS70318F-page 104 © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — INT2IF — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT1IF CNIF AC1IF MI2C1IF SI2C1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IF: External Interrupt
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-7: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — PSEMIF — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 Unimplemented: Read as ‘0’ bit 9 PSEMIF: PWM Special Event Match Interrupt Flag Status bit 1 =
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-9: IFS5: INTERRUPT FLAG STATUS REGISTER 5 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 PWM2IF PWM1IF — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 PWM2IF: PWM2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt reque
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-10: IFS6: INTERRUPT FLAG STATUS REGISTER 6 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 ADCP1IF ADCP0IF — — — — AC4IF AC3IF bit 15 bit 8 R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 AC2IF — — — — — PWM4IF PWM3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADCP1IF: ADC Pair 1 Conversion Done Interrupt Flag Status
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-11: IFS7: INTERRUPT FLAG STATUS REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — ADCP6IF ADCP5IF ADCP4IF ADCP3IF ADCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-5 Unimplemented: Read as ‘0’ bit 4 ADCP6IF: ADC Pair 6 Conversio
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-12: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — ADIE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-12: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-13: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — INT2IE — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT1IE CNIE AC1IE MI2C1IE SI2C1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 INT2IE: External Interr
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-14: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — PSEMIE — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 Unimplemented: Read as ‘0’ bit 9 PSEMIE: PWM Special Event Match Interrupt Enable bit 1 = I
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-16: IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 PWM2IE PWM1IE — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 PWM2IE: PWM2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-17: IEC6: INTERRUPT ENABLE CONTROL REGISTER 6 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 ADCP1IE ADCP0IE — — — — AC4IE AC3IE bit 15 bit 8 R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 AC2IE — — — — — PWM4IE PWM3IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ADCP1IE: ADC Pair 1 Conversion Done Interrupt Enable bi
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-18: IEC7: INTERRUPT ENABLE CONTROL REGISTER 7 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — ADCP6IE ADCP5IE ADCP4IE ADCP3IE ADCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-5 Unimplemented: Read as ‘0’ bit 4 ADCP6IE: ADC Pair 6 Conver
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-19: U-0 IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 R/W-1 — R/W-0 R/W-0 T1IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 OC1IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 IC1IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 INT0IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1IP<2:0>: Timer1 Interrupt P
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-20: U-0 IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 R/W-1 — R/W-0 R/W-0 T2IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 OC2IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 IC2IP<2:0> R/W-0 U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bi
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-21: U-0 IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 R/W-1 — R/W-0 R/W-0 U1RXIP<2:0> U-0 R/W-1 — R/W-0 R/W-0 SPI1IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 SPI1EIP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 T3IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U1RXIP<2:0>: UART1 Receiver
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-22: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 ADIP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 U1TXIP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 ADIP<2:0>: ADC1 Conversion Complete Interrupt
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-23: U-0 IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 R/W-1 — R/W-0 R/W-0 CNIP<2:0> U-0 R/W-1 — R/W-0 R/W-0 AC1IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 MI2C1IP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 SI2C1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNIP<2:0>: Change Notificat
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-24: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 INT1IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-26: IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 R/W-0 PSEMIP<2:0> U-0 U-0 U-0 U-0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 PSEMIP<2:0>: PWM Special Event
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-28: U-0 IPC23: INTERRUPT PRIORITY CONTROL REGISTER 23 R/W-1 — R/W-0 R/W-0 U-0 PWM2IP R/W-1 — R/W-0 R/W-0 PWM1IP<2:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 PWM2IP<2:0>: PWM2 Interrupt Priority bits 111 =
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-29: IPC24: INTERRUPT PRIORITY CONTROL REGISTER 24 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 R/W-0 U-0 PWM4IP — R/W-1 R/W-0 R/W-0 PWM3IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 PWM4IP<2:0>: PWM4 Interrupt Priority bits 111
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-30: U-0 IPC25: INTERRUPT PRIORITY CONTROL REGISTER 25 R/W-1 — R/W-0 R/W-0 AC2IP<2:0> U-0 U-0 U-0 U-0 — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 AC2IP<2:0>: Analog Comparator 2 Interrupt Priority bi
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-31: IPC26: INTERRUPT PRIORITY CONTROL REGISTER 26 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/W-1 — R/W-0 AC4IP<2:0> R/W-0 U-0 — R/W-1 R/W-0 R/W-0 AC3IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-7 Unimplemented: Read as ‘0’ bit 6-4 AC4IP<2:0>: Analog Comparator 4 Interrupt Pr
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-32: U-0 IPC27: INTERRUPT PRIORITY CONTROL REGISTER 27 R/W-1 — R/W-0 R/W-0 ADCP1IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 ADCP0IP<2:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as ‘0’ bit 14-12 ADCP1IP<2:0>: ADC Pa
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-33: U-0 IPC28: INTERRUPT PRIORITY CONTROL REGISTER 28 R/W-1 — R/W-0 R/W-0 ADCP5IP<2:0> U-0 R/W-1 — R/W-0 R/W-0 ADCP4IP<2:0> bit 15 bit 8 U-0 R/W-1 — R/W-0 ADCP3IP<2:0> R/W-0 U-0 R/W-1 — R/W-0 R/W-0 ADCP2IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 ADCP5IP<2:0>: ADC P
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-34: IPC29: INTERRUPT PRIORITY CONTROL REGISTER 29 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-1 R/W-0 R/W-0 ADCP6IP<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 ADCP6IP<2:0>: ADC Pair 6 Conv
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 7-35: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 U-0 U-0 U-0 — — — — R-0 R-0 R-0 R-0 ILR<3:0> bit 15 bit 8 U-0 R-0 R-0 — R-0 R-0 R-0 R-0 R-0 VECNUM<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11-8 ILR<3:0>: New CPU Interrupt Priority Level bits 1111 = CPU Interrup
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 7.4 Interrupt Setup Procedures 7.4.1 7.4.3 INITIALIZATION Complete the following steps to configure an interrupt source at initialization: 1. 2. Set the NSTDIS bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 8.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 8.1 CPU Clocking System The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 devices provide six system clock options: • • • • • • Fast RC (FRC) Oscillator FRC Oscillator with PLL Primary (XT, HS or EC) Oscillator Primary Oscillator with PLL Low-Power RC (LPRC) Oscillator FRC Oscillator with Postscaler 8.1.1 The FRC frequency depends on the FRC accuracy (see Table 24-20) and the value of the FRC Oscillator Tuning register (see Register 8-4). 8.1.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 8.1.3 PLL CONFIGURATION The primary oscillator and internal FRC oscillator can optionally use an on-chip PLL to obtain higher speeds of operation. The PLL provides significant flexibility in selecting the device operating speed. A block diagram of the PLL is shown in Figure 8-2. The output of the primary oscillator or FRC, denoted as ‘FIN’, is divided down by a prescale factor (N1) of 2, 3, ...
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 8.2 Auxiliary Clock Generation The auxiliary clock generation is used for a peripherals that need to operate at a frequency unrelated to the system clock such as a PWM or ADC. The primary oscillator and internal FRC oscillator sources can be used with an auxiliary PLL to obtain the auxiliary clock. The auxiliary PLL has a fixed 16x multiplication factor.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 8.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER(1,2) (CONTINUED) bit 3 CF: Clock Fail Detect bit (read/clear by application) 1 = FSCM has detected clock failure 0 = FSCM has not detected clock failure bit 2-1 Unimplemented: Read as ‘0’ bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<2:0> bits 0 = Oscillator switch is complete Note 1: 2: 3: Writes to this register require an unlock sequence.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 8-2: R/W-0 ROI bit 15 CLKDIV: CLOCK DIVISOR REGISTER(1) R/W-0 R/W-1 DOZE<2:0> Legend: R = Readable bit -n = Value at POR bit 14-12 bit 11 bit 10-8 bit 7-6 bit 5 bit 4-0 Note 1: 2: R/W-0 DOZEN(2) R/W-0 R/W-0 FRCDIV<2:0> R/W-0 bit 8 R/W-0 R/W-1 PLLPOST<1:0> bit 7 bit 15 R/W-1 U-0 — R/W-0 R/W-0 R/W-0 PLLPRE<4:0> R/W-0 R/W-0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unk
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 8-3: PLLFBD: PLL FEEDBACK DIVISOR REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — PLLDIV<8> bit 15 bit 8 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 PLLDIV<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8-0 PLLDIV<8:0>: PLL Feedback Diviso
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 8-4: OSCTUN: FRC OSCILLATOR TUNING REGISTER(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TUN<5:0>(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(2) 011111 = Center fr
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 ACLKCON: AUXILIARY CLOCK DIVISOR CONTROL REGISTER(1) REGISTER 8-5: R/W-0 R-0 R/W-1 U-0 U-0 ENAPLL APLLCK SELACLK — — R/W-1 R/W-1 R/W-1 APSTSCLR<2:0> bit 15 bit 0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 ASRCSEL FRCSEL — — — — — — bit 7 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ENAPLL: Auxiliary PLL Enable bit 1
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 8-6: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 ROON — ROSSLP ROSEL R/W-0 R/W-0 R/W-0 R/W-0 RODIV<3:0>(1) bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ROON: Reference Oscillator Output Enable bit 1 = Reference oscillator
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 8.5 Clock Switching Operation Users can switch applications among any of the four clock sources (primary, LP, FRC and LPRC) under software control at any time. To limit the possible side effects of this flexibility, dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices have a safeguard lock built into the switch process. Note: 8.5.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 9.0 POWER-SAVING FEATURES Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 9. “Watchdog Timer and Power-Saving Modes” (DS70196) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 9.2.2 IDLE MODE The following occur in Idle mode: • The CPU stops executing instructions • The WDT is automatically cleared • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9.4 “Peripheral Module Disable”).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 9-1: U-0 PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 U-0 — — R/W-0 T3MD R/W-0 T2MD R/W-0 T1MD U-0 — R/W-0 U-0 (1) PWMMD — bit 15 bit 8 R/W-0 U-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 I2C1MD — U1MD — SPI1MD — — ADCMD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 T3MD: Timer3
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 9-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — IC2MD IC1MD bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — OC2MD OC1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-10 Unimplemented: Read as ‘0’ bit 9 IC2MD: Input Capture 2 Module Dis
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 9-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 — — — — — CMPMD — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10 CMPMD: Analog Comparator Module Disable bit 1 = An
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 9-5: PMD6: PERIPHERAL MODULE DISABLE CONTROL REGISTER 6 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — PWM4MD PWM3MD PWM2MD PWM1MD bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11 PWM4MD: PWM Generator 4 Modu
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 9-6: PMD7: PERIPHERAL MODULE DISABLE CONTROL REGISTER 7 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — CMP4MD CMP3MD CMP2MD CMP1MD bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-12 Unimplemented: Read as ‘0’ bit 11 CMP4MD: Analog Comparator 4
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318F-page 152 © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 10.0 I/O PORTS Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 10. “I/O Ports” (DS70193) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available on Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 10.2 Open-Drain Configuration In addition to the PORT, LAT and TRIS registers for data control, some digital-only port pins can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 10.6 Peripheral Pin Select Peripheral pin select configuration enables peripheral set selection and placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, programmers can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device. The peripheral pin select configuration feature operates over a fixed subset of digital I/O pins.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 10-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO Function) Function Name Register Configuration Bits INT1 RPINR0 INT1R<5:0> External Interrupt 2 INT2 RPINR1 INT2R<5:0> Timer1 External Clock T1CK RPINR2 T1CKR<5:0> Timer2 External Clock T2CK RPINR3 T2CKR<5:0> Timer3 External Clock T3CK RPINR3 T3CKR<5:0> Input Capture 1 IC1 RPINR7 IC1R<5:0> Input Capture 2 IC2 RPINR7 IC2R<5:0> Input Name External Interrupt 1 Output Compare Fault A
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 10.6.2.2 Output Mapping FIGURE 10-3: In contrast to inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 10.6.2.3 Virtual Pins dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices support four virtual RPn pins (RP32, RP33, RP34 and RP35), which are identical in functionality to all other RPn pins, with the exception of pinouts. These four pins are internal to the devices and are not connected to a physical device pin. These pins provide a simple way for inter-peripheral connection without utilizing a physical pin.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 10.7 Peripheral Pin Select Registers The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices implement 34 registers for remappable peripheral configuration: Not all output remappable peripheral registers are implemented on all devices. See the specific register description for further details.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 INT2R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 INT2R<5:0>: Assign External Inter
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 T3CKR<5:0> bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 T2CKR<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 T3CKR<5:0>: Assign Timer3
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-4: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IC2R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 IC1R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 IC2R<5:0>: Assign Input Cap
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-5: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OCFAR<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 OCFAR<5:0>: Assign Output Captu
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-6: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U1CTSR<5:0> bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U1RXR<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 U1CTSR<5:0>: Assign UA
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-7: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SCK1R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SDI1R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 SCK1R<5:0>: Assign SPI1
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-8: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SS1R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 SS1R<5:0>: Assign SPI1 Slave Sel
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-9: RPINR29: PERIPHERAL PIN SELECT INPUT REGISTER 29 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLT1R<5:0> bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FLT1R<5:0>: Assign PWM Fault
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-10: RPINR30: PERIPHERAL PIN SELECT INPUT REGISTER 30 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLT3R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLT2R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FLT3R<5:0>: Assign PWM F
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-11: RPINR31: PERIPHERAL PIN SELECT INPUT REGISTER 31 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLT5R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLT4R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FLT5R<5:0>: Assign PWM F
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-12: RPINR32: PERIPHERAL PIN SELECT INPUT REGISTER 32 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLT7R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLT6R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 FLT7R<5:0>: Assign PWM F
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-13: RPINR33: PERIPHERAL PIN SELECT INPUT REGISTER 33 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SYNCI1R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 FLT8R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 SYNCI1R<5:0>: Assign P
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-14: RPINR34: PERIPHERAL PIN SELECT INPUT REGISTER 34 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 SYNCI2R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 SYNCI2R<5:0>: Assign PWM Maste
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-16: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP3R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP2R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP3R<5:0>: Peripheral Output
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-18: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP7R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP6R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP7R<5:0>: Peripheral Output
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-20: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP11R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP10R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP11R<5:0>: Peripheral Out
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-22: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP15R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP14R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP15R<5:0>: Peripheral Out
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-24: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP19R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP18R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP19R<5:0>: Peripheral Out
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-26: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP23R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP22R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP23R<5:0>: Peripheral O
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-28: RPOR13: PERIPHERAL PIN SELECT OUTPUT REGISTER 13 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP27R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP26R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP27R<5:0>: Peripheral O
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 10-30: RPOR16: PERIPHERAL PIN SELECT OUTPUT REGISTER 16 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP33R<5:0> bit 15 bit 8 U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RP32R<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13-8 RP33R<5:0>: Peripheral O
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 11.0 TIMER1 The unique features of Timer1 allow it to be used for Real-Time Clock (RTC) applications. A block diagram of Timer1 is shown in Figure 11-1. Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 11.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE R/W-0 R/W-0 TCKPS<1:0> U-0 R/W-0 R/W-0 U-0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 U
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 12.0 TIMER2/3 FEATURES Timer2 is a Type B timer that offers the following major features: Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 11. “Timers” (DS70205) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available on the Microchip web site (www.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 The Timer2/3 module can operate in one of the following modes: • Timer mode • Gated Timer mode • Synchronous Counter mode In Timer and Gated Timer modes, the input clock is derived from the internal instruction cycle clock (FCY). In Synchronous Counter mode, the input clock is derived from the external clock input at the TxCK pin.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 12-3: 32-BIT TIMER BLOCK DIAGRAM Gate Sync Falling Edge Detect 1 Set TyIF Flag PRy PRx 0 Equal Comparator FCY Prescaler (/n) lsw 00 TCKPS<1:0> Prescaler (/n) TGATE 10 Sync TMRx(1) msw TMRy(2) Reset x1 TxCK TCKPS<1:0> TGATE TMRyHLD TCS Data Bus <15:0> Note 1: Timerx is a Type B Timer (x = 2). 2: Timery is a Type C Timer (y = 3). © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 12-1: TxCON: TIMER CONTROL REGISTER (x = 2) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE R/W-0 R/W-0 TCKPS<1:0> R/W-0 U-0 R/W-0 U-0 T32 — TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timerx On bit When T32 = 1 (in 32-bit Timer mode): 1 = Starts 32-bit
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 12-2: R/W-0 TyCON: TIMER CONTROL REGISTER (y = 3) U-0 TON(2) — R/W-0 (1) TSIDL U-0 U-0 U-0 U-0 U-0 — — — — — bit 15 bit 8 U-0 R/W-0 — TGATE(2) R/W-0 R/W-0 TCKPS<1:0>(2) U-0 — U-0 R/W-0 U-0 — TCS(2) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timery On bit(2) 1 = Starts 16-bit Timery 0 = Stops 16-bit
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318F-page 188 © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 13.0 INPUT CAPTURE Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 12. “Input Capture” (DS70198) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 13.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 14.0 OUTPUT COMPARE Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 13. “Output Compare” (DS70209) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 14.1 Output Compare Modes application must disable the associated timer when writing to the Output Compare Control registers to avoid malfunctions. Configure the Output Compare modes by setting the appropriate Output Compare Mode (OCM<2:0>) bits in the Output Compare Control (OCxCON<2:0>) register. Table 14-1 lists the different bit settings for the Output Compare modes. Figure 14-2 illustrates the output compare operation for various modes.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 14-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER (x = 1, 2) U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 — — OCSIDL — — — — — bit 15 bit 8 U-0 U-0 U-0 R-0, HC R/W-0 — — — OCFLT OCTSEL R/W-0 R/W-0 R/W-0 OCM<2:0> bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bi
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318F-page 194 © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 15.0 HIGH-SPEED PWM Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 43. “High- Speed PWM” (DS70323) in the “dsPIC33F/ PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 15.2 Feature Description The PWM module is designed for applications that require: • High-resolution at high PWM frequencies • The ability to drive Standard, Edge-Aligned, Center-Aligned Complementary mode, and Push-Pull mode outputs • The ability to create multiphase PWM outputs For Center-Aligned mode, the duty cycle, period phase and dead-time resolutions will be 8.32 ns. Two common, medium power converter topologies are push-pull and half-bridge.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 15-1: SIMPLIFIED CONCEPTUAL BLOCK DIAGRAM OF HIGH-SPEED PWM PWMCONx Pin and Mode Control LEBCONx Control for Blanking External Input Signals TRGCONx ADC Trigger Control Dead-Time Control ALTDTRx, DTRx PWM Enable and Mode Control PTCON MDC Master Duty Cycle Register PDC1 MUX Latch PWM GEN 1 Comparator Channel 1 Dead-Time Generator PWM1H Channel 2 Dead-Time Generator PWM2H PWM1L Timer Phase 16-bit Data Bus Latch PWM GEN 2 Comparator T
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 15-2: PARTITIONED OUTPUT PAIR, COMPLEMENTARY PWM MODE Phase Offset TMR < PDC PWM Dead-Time Timer/Counter Override Logic Logic M U X PWMXH M U X PWMXL Duty Cycle Comparator PWM Duty Cycle Register Channel Override Values Fault Override Values Fault Pin 15.3 Fault Pin Assignment Logic Fault Active Control Registers The following registers control the operation of the high-speed PWM module.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-1: PTCON: PWM TIME BASE CONTROL REGISTER R/W-0 PTEN bit 15 U-0 — R/W-0 PTSIDL HS/HC-0 SESTAT R/W-0 SEIEN R/W-0 EIPU(1) R/W-0 SYNCEN(1) bit 7 U-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5-4 bit 3-0 Note 1: R/W-0 R/W-0 SEVTPS<3:0>(1) bit 0 Legend: R = Readable bit -n = Value at POR bit 15 SYNCSRC<1:0>(1) — R/W-0 R/W-0 (1) SYNCPOL SYNCOEN(1) bit 8 HC = Hardware Clearable bit W
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-2: PTCON2: PWM CLOCK DIVIDER SELECT REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — U-0 — U-0 — U-0 R/W-0 R/W-0 R/W-0 (1) — PCLKDIV<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 PCLKDIV<2:0>: PWM Input Clock P
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-4: R/W-0 SEVTCMP: PWM SPECIAL EVENT COMPARE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP <12:5> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEVTCMP <4:0> U-0 U-0 U-0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 SEVTCMP<12:0>: Special Event Compare Count Value bits bit 2-0 Unimplemented: Read
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-6: PWMCONx: PWMx CONTROL REGISTER HS/HC-0 HS/HC-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTSTAT(1) CLSTAT(1) TRGSTAT FLTIEN CLIEN TRGIEN ITB(3) MDCS(3) bit 15 bit 8 R/W-0 R/W-0 DTC<1:0> U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — CAM(2,3) XPRES(4) IUE bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-6: PWMCONx: PWMx CONTROL REGISTER (CONTINUED) bit 2 CAM: Center-Aligned Mode Enable bit(2,3) 1 = Center-Aligned mode is enabled 0 = Center-Aligned mode is disabled bit 1 XPRES: External PWM Reset Control bit(4) 1 = Current-limit source resets time base for this PWM generator if it is in Independent Time Base mode 0 = External pins do not affect PWM time base bit 0 IUE: Immediate Update Enable bit 1 = Updates to the active MDC/PDCx/SDCx registe
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-7: R/W-0 PDCx: PWMx GENERATOR DUTY CYCLE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDCx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PDCx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown PDCx<15:0>: PWM Generator # Duty Cycle Value bits Note 1: In Independent PWM m
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-9: R/W-0 PHASEx: PWMx PRIMARY PHASE SHIFT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHASEx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown PHASEx<15:0>: PWM Phase Shift Value or Independent Time Base Period for th
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-10: SPHASEx: PWMx SECONDARY PHASE SHIFT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPHASEx<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPHASEx<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-0 x = Bit is unknown SPHASEx<15:0>: Secondary Phase Offset for PWMxL Output Pin bits (use
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 .
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-13: TRGCONx: PWMx TRIGGER CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 TRGDIV<3:0> U-0 U-0 U-0 U-0 — — — — bit 15 bit 8 R/W-0 U-0 DTM(1) — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSTRT<5:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-12 TRGDIV<3:0>: Trigger # Output Divider bits 1111 = Trigger ou
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-14: IOCONx: PWMx I/O CONTROL REGISTER R/W-0 R/W-0 PENH PENL R/W-0 POLH R/W-0 POLL R/W-0 R/W-0 PMOD<1:0>(1) R/W-0 R/W-0 OVRENH OVRENL bit 15 bit 8 R/W-0 R/W-0 R/W-0 OVRDAT<1:0> R/W-0 FLTDAT<1:0> R/W-0 R/W-0 CLDAT<1:0> R/W-0 R/W-0 SWAP OSYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PENH:
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-14: IOCONx: PWMx I/O CONTROL REGISTER (CONTINUED) bit 3-2 CLDAT<1:0>: State(2) for PWMxH and PWMxL Pins if CLMODE is Enabled bits FCLCONx = 0: Normal Fault mode: If current-limit active, then CLDAT<1> provides state for PWMxH. If current-limit active, then CLDAT<0> provides state for PWMxL. FCLCONx = 1: Independent Fault mode: CLDAT<1:0> is ignored.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-15: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CLSRC<4:0>(2,3) IFLTMOD R/W-0 R/W-0 CLPOL(1) CLMOD bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTSRC<4:0>(2,3) R/W-0 R/W-0 (1) FLTPOL R/W-0 FLTMOD<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IFLT
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-15: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER (CONTINUED) bit 7-3 FLTSRC<4:0>: Fault Control Signal Source Select for PWM Generator # bits(2,3) 11111 = Reserved • • • 01000 = Reserved 00111 = Fault 8 00110 = Fault 7 00101 = Fault 6 00100 = Fault 5 00011 = Fault 4 00010 = Fault 3 00001 = Fault 2 00000 = Fault 1 bit 2 FLTPOL: Fault Polarity for PWM Generator # bit(1) 1 = The selected Fault source is active-low 0 = The selected Fault source
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-16: TRIGx: PWMx PRIMARY TRIGGER COMPARE VALUE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGCMP<12:5> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGCMP<4:0> U-0 U-0 U-0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 TRGCMP<12:0>: Trigger Control Value bits When primary PWM fu
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-18: LEBCONx: LEADING-EDGE BLANKING CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHR PHF PLR PLF FLTLEBEN CLLEBEN R/W-0 R/W-0 LEB<6:5> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEB<4:0> U-0 U-0 U-0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PHR: PWMxH Rising Edge Trigger E
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 15-19: PWMCAPx: PRIMARY PWMx TIME BASE CAPTURE REGISTER R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 PWMCAP<12:5>(1,2) bit 15 bit 8 R-0 R-0 R-0 R-0 R-0 PWMCAP<4:0>(1,2) U-0 U-0 U-0 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-3 PWMCAP<12:0>: Captured PWM Time Base Value bits(1,2) The value in this registe
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318F-page 216 © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 16.0 SERIAL PERIPHERAL INTERFACE (SPI) Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 18. “Serial Peripheral Interface (SPI)” (DS70206) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 SPIEN — SPISIDL — — — — — bit 15 bit 8 U-0 R/C-0 U-0 U-0 U-0 U-0 R-0 R-0 — SPIROV — — — — SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 SPIEN: SPIx Enable bit 1 = Enab
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — DISSCK DISSDO MODE16 SMP CKE(1) bit 15 bit 8 R/W-0 R/W-0 SSEN(3) CKP R/W-0 R/W-0 MSTEN R/W-0 R/W-0 R/W-0 (2) R/W-0 PPRE<1:0>(2) SPRE<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) bit 4-2 SPRE<2:0>: Secondary Prescale bits (Master mode)(2) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 • • • 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)(2) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: 2: 3: The CKE bit is not used in the Framed SPI modes.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 16-3: SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 FRMEN SPIFSD FRMPOL — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 U-0 — — — — — — FRMDLY — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support enabled (
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318F-page 222 © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 17.0 INTER-INTEGRATED CIRCUIT (I2C™) Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 19. “Inter-Integrated Circuit (I2C™)” (DS70195) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 17-1: I2C™ BLOCK DIAGRAM (X = 1) Internal Data Bus I2CxRCV Read SCLx Shift Clock I2CxRSR LSb SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSb Read Shift Clock Reload Control BRG Down Counter Write I2CxBRG Read TCY/2 DS70318F-page
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 17.2 I2C Registers I2CxCON and I2CxSTAT are control and status registers. The I2CxCON register is readable and writable. The lower six bits of I2CxSTAT are read-only.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HS = Hardware Settable bit HC = Hardware Clearable bit -n = Value at
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that is transmitted when the software initiates an Acknowledge sequence.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HSC R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0, HS R/C-0, HS R-0, HSC IWCOL I2COV D_A R/C-0, HSC R/C-0, HSC P R-0, HSC R-0, HSC R-0, HSC R_W RBF TBF S bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit HS = Hardware Settable bit HSC = Hardware Settable/Clearable -n = Val
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 17-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0 R/W-0 AMSK<9:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 AMSK<9:0>: Mask for Address
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 18.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual”, which is available on the Microchip web site (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 18-1: R/W-0 UxMODE: UARTx MODE REGISTER U-0 UARTEN(1) — R/W-0 USIDL R/W-0 IREN (2) R/W-0 U-0 RTSMD — R/W-0 R/W-0 UEN<1:0> bit 15 bit 8 R/W-0 HC R/W-0 R/W-0, HC R/W-0 R/W-0 WAKE LPBACK ABAUD URXINV BRGH R/W-0 R/W-0 PDSEL<1:0> R/W-0 STSEL bit 7 bit 0 Legend: HC = Hardware Clearable R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 18-2: R/W-0 UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 UTXISEL1 UTXINV R/W-0 UTXISEL0 U-0 — R/W-0, HC UTXBRK R/W-0 (1) UTXEN R-0 R-1 UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 URXISEL<1:0> R/W-0 R-1 R-0 R-0 R/C-0 R-0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: HC = Hardware Clearable bit C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318F-page 236 © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 19.0 HIGH-SPEED 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 44.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 19-1: ADC BLOCK DIAGRAM FOR dsPIC33FJ06GS101 DEVICES WITH ONE SAR Even Numbered Inputs with Dedicated Sample and Hold (S&H) Circuits AN0 Eight 16-bit Registers Bus Interface SAR Core Data Format AN2 AN1 Shared Sample and Hold AN3 AN6 AN7 DS70318F-page 238 © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 19-2: ADC BLOCK DIAGRAM FOR dsPIC33FJ06GS102 DEVICES WITH ONE SAR Even Numbered Inputs with Dedicated Sample and Hold (S&H) Circuits AN0 Eight 16-bit Registers Bus Interface SAR Core Data Format AN2 AN1 Shared Sample and Hold AN3 AN4 AN5 © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 19-3: ADC BLOCK DIAGRAM FOR dsPIC33FJ06GS202 DEVICES WITH ONE SAR Even Numbered Inputs with Dedicated Sample and Hold (S&H) Circuits AN0 AN12(1) (EXTREF) Eight 16-bit Registers Bus Interface SAR Core Data Format AN2 AN1 Shared Sample and Hold AN3 AN4 AN5 AN13(2) (INTREF) Note 1: AN12 (EXTREF) is an internal analog input.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 19-4: ADC BLOCK DIAGRAM FOR dsPIC33FJ16GS402/404 DEVICES WITH ONE SAR Even Numbered Inputs with Dedicated Sample and Hold (S&H) Circuits AN0 AN2 Ten 16-bit Registers Bus Interface SAR Core Data Format AN4 AN1 AN3 Shared Sample and Hold AN5 AN6 AN7 © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 19-5: ADC BLOCK DIAGRAM FOR dsPIC33FJ16GS502 DEVICES WITH TWO SARS Even Numbered Inputs with Dedicated Sample and Hold (S&H) Circuits AN0 Data Format SAR Core Five 16-bit Registers Data Format AN2 Five 16-bit Registers AN4 AN6 Bus Interface Even numbered inputs with shared S&H AN12(1) (EXTREF) AN1 Odd Numbered Inputs with Shared S&H AN3 AN5 SAR AN7 Core AN13(2) (INTREF) Note 1: AN12 (EXTREF) is an internal analog input.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 19-6: ADC BLOCK DIAGRAM FOR dsPIC33FJ16GS504 DEVICES WITH TWO SARS Even Numbered Inputs with Dedicated Sample and Hold (S&H) Circuits AN0 Data Format SAR Core Seven 16-bit Registers Data Format AN2 Seven 16-bit Registers AN4 AN6 AN8 Bus Interface Even Numbered Inputs with Shared S&H AN10 AN12(1) (EXTREF) AN1 Odd Numbered Inputs with Shared S&H SAR AN3 Core AN5 AN7 AN9 AN11 AN13(2) (INTREF) Note 1: AN12 (EXTREF) is an internal analog
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 19.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-1: R/W-0 ADCON: ANALOG-TO-DIGITAL CONTROL REGISTER U-0 ADON — R/W-0 ADSIDL R/W-0 SLOWCLK (1) U-0 R/W-0 U-0 R/W-0 — GSWTRG — FORM(1) bit 15 bit 8 R/W-0 EIE(1) R/W-0 R/W-0 R/W-0 U-0 ORDER(1,2) SEQSAMP(1,2) ASYNCSAMP(1) R/W-0 — R/W-1 R/W-1 ADCS<2:0>(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bi
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-1: ADCON: ANALOG-TO-DIGITAL CONTROL REGISTER (CONTINUED) bit 3 Unimplemented: Read as ‘0’ bit 2-0 ADCS<2:0>: Analog-to-Digital Conversion Clock Divider Select bits(1) 111 = FADC/8 110 = FADC/7 101 = FADC/6 100 = FADC/5 011 = FADC/4 (default) 010 = FADC/3 001 = FADC/2 000 = FADC/1 Note 1: This control bit can only be changed while ADC is disabled (ADON = 0). 2: This bit is only available on devices with one SAR.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-2: ADSTAT: ANALOG-TO-DIGITAL STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS R/C-0, HS — P6RDY P5RDY P4RDY P3RDY P2RDY P1RDY P0RDY bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR C = Clearable bit ‘1’ = Bit is set HS = Hardware Settable bit ‘0’ = Bit is clear
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-3: R/W-0 ADBASE: ANALOG-TO-DIGITAL BASE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADBASE<15:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 ADBASE<7:1> — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-1 ADBASE<15:1>: This register contains the base address of the user’s ADC In
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-5: ADCPC0: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 0 R/W-0 R/W-0 R/W-0 IRQEN1 PEND1 SWTRG1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC1<4:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 IRQEN0 PEND0 SWTRG0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC0<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IRQEN1: I
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-5: ADCPC0: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 0 (CONTINUED) bit 12-8 TRGSRC1<4:0>: Trigger 1 Source Selection bits Selects trigger source for conversion of analog channels AN3 and AN2.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-5: bit 4-0 Note 1: ADCPC0: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 0 (CONTINUED) TRGSRC0<4:0>: Trigger 0 Source Selection bits Selects trigger source for conversion of analog channels AN1 and AN0.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-6: ADCPC1: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 IRQEN3(1) PEND3(1) SWTRG3(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC3<4:0>(1) bit 15 bit 8 R/W-0 R/W-0 IRQEN2(2) PEND2 (2) R/W-0 R/W-0 (2) SWTRG2 R/W-0 R/W-0 TRGSRC2<4:0> R/W-0 R/W-0 (2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit i
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-6: ADCPC1: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 1 (CONTINUED) bit 12-8 TRGSRC3<4:0>: Trigger 3 Source Selection bits(1) Selects trigger source for conversion of analog channels AN7 and AN6.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-6: bit 4-0 ADCPC1: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 1 (CONTINUED) TRGSRC2<4:0>: Trigger 2 Source Selection bits Selects trigger source for conversion of analog channels AN5 and AN4.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-7: ADCPC2: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 IRQEN5 PEND5 SWTRG5 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC5<4:0> bit 15 bit 8 R/W-0 R/W-0 R/W-0 IRQEN4 PEND4 SWTRG4 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC4<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 IRQEN5: I
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-7: ADCPC2: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 2 (CONTINUED) bit 12-8 TRGSRC5<4:0>: Trigger 5 Source Selection bits Selects trigger source for conversion of analog channels AN11 and AN10.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-7: bit 4-0 Note 1: 2: ADCPC2: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 2 (CONTINUED) TRGSRC4<4:0>: Trigger 4 Source Selection bits Selects trigger source for conversion of analog channels AN9 and AN8.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-8: ADCPC3: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 3(1) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 IRQEN6 PEND6 SWTRG6 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRGSRC6<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 19-8: bit 4-0 Note 1: 2: ADCPC3: ANALOG-TO-DIGITAL CONVERT PAIR CONTROL REGISTER 3(1) (CONTINUED) TRGSRC6<4:0>: Trigger 6 Source Selection bits Selects trigger source for conversion of analog channels AN13 and AN12.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318F-page 260 © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 20.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 20.3 Module Applications 20.5 Interaction with I/O Buffers This module provides a means for the SMPS dsPIC DSC devices to monitor voltage and currents in a power conversion application. The ability to detect transient conditions and stimulate the dsPIC DSC processor and/or peripherals, without requiring the processor and ADC to constantly monitor voltages or currents, frees the dsPIC DSC to perform other tasks.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 20-1: CMPCONx: COMPARATOR CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 CMPON — CMPSIDL — — — — DACOE bit 15 bit 8 R/W-0 R/W-0 INSEL<1:0> R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0 EXTREF — CMPSTAT — CMPPOL RANGE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CMPON: Comparator Operating Mo
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 REGISTER 20-2: CMPDACx: COMPARATOR DAC CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0 R/W-0 CMREF<9:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CMREF<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Reserved: Read as ‘0’ bit 9-0 CMREF<9:0>: Comparator Reference Vol
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 21.0 SPECIAL FEATURES 21.1 Note 1: This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest “dsPIC33F/PIC24H Family Reference Manual” sections.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 21-2: dsPIC33F CONFIGURATION BITS DESCRIPTION Bit Field Register RTSP Effect Description BWRP FBS Immediate Boot Segment Program Flash Write Protection bit 1 = Boot segment can be written 0 = Boot segment is write-protected BSS<2:0> FBS Immediate Boot Segment Program Flash Code Protection Size bits x11 = No boot program Flash segment Boot space is 256 instruction words (except interrupt vectors) 110 = Standard security; boot program Flash segm
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 21-2: Bit Field dsPIC33F CONFIGURATION BITS DESCRIPTION (CONTINUED) Register RTSP Effect POSCMD<1:0> FOSC Immediate Primary Oscillator Mode Select bits 11 = Primary oscillator disabled 10 = HS Crystal Oscillator mode 01 = XT Crystal Oscillator mode 00 = EC (External Clock) mode FWDTEN FWDT Immediate Watchdog Timer Enable bit 1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled; clearing the SWDTEN bit in the RCON register will ha
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 21.2 On-Chip Voltage Regulator 21.3 BOR: Brown-Out Reset The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices power their core digital logic at a nominal 2.5V. This can create a conflict for designs that are required to operate at a higher typical voltage, such as 3.3V.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 21.4 Watchdog Timer (WDT) 21.4.2 For dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. 21.4.1 PRESCALER/POSTSCALER The nominal WDT clock source from LPRC is 32 kHz. This feeds a prescaler than can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the WDTPRE Configuration bit.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 21.5 JTAG Interface The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices implement a JTAG interface, which supports boundary scan device testing, as well as in-circuit programming. Detailed information on this interface will be provided in future revisions of the document. 21.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 21.8 Code Protection and CodeGuard™ Security The code protection features are controlled by the Configuration registers: FBS and FGS. The dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices offer the intermediate implementation of CodeGuard™ Security. CodeGuard Security enables multiple parties to securely share resources (memory, interrupts and peripherals) on a single chip.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318F-page 272 © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 22.0 Note: INSTRUCTION SET SUMMARY This data sheet summarizes the features of the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the latest sections in the “dsPIC33F/PIC24H Family Reference Manual”, which are available on the Microchip web site (www.microchip.com). The dsPIC33F instruction set is identical to that of the dsPIC30F.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Most instructions are a single word. Certain double-word instructions are designed to provide all the required information in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. The double-word instructions execute in two instruction cycles.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 22-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED) Field Description Wm*Wm Multiplicand and Multiplier Working register pair for Square instructions ∈ {W4 * W4,W5 * W5,W6 * W6,W7 * W7} Wm*Wn Multiplicand and Multiplier Working register pair for DSP instructions ∈ {W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7} Wn One of 16 Working registers ∈ {W0..W15} Wnd One of 16 Destination Working registers ∈ {W0...
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 22-2: Base Instr # 1 2 3 4 INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR Assembly Syntax # of # of Words Cycles Description Status Flags Affected ADD Acc Add Accumulators 1 1 ADD f f = f + WREG 1 1 OA,OB,SA,SB C,DC,N,OV,Z ADD f,WREG WREG = f + WREG 1 1 C,DC,N,OV,Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C,DC,N,OV,Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C,DC,N,OV,Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C,DC,N,OV,Z
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 22-2: Base Instr # 10 11 12 13 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTSC BTSS BTST BTSTS Assembly Syntax Description # of # of Words Cycles Status Flags Affected BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 (2 or 3) None BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 (2 or 3) None BTSS f,#bit4 Bit Test f, Skip if Set 1 1 (2 or 3) None BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 (2 or 3) None BTST f,#bit4
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 22-2: Base Instr # 29 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic DIV Assembly Syntax # of # of Words Cycles Description Status Flags Affected DIV.S Wm,Wn Signed 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N,Z,C,OV DIV.U Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N,Z,C,OV DIV.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 22-2: Base Instr # 48 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic MPY Assembly Syntax Description # of # of Words Cycles Status Flags Affected MPY Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB MPY Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator 1 1 OA,OB,OAB, SA,SB,SAB 49 MPY.N MPY.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 22-2: Base Instr # 66 67 INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic RRNC SAC Assembly Syntax # of # of Words Cycles Description Status Flags Affected RRNC f f = Rotate Right (No Carry) f 1 1 RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N,Z N,Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N,Z SAC Acc,#Slit4,Wdo Store Accumulator 1 1 None SAC.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 23.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 23.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 23.7 MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 23.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 23.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 24.0 ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 24.1 DC Characteristics TABLE 24-1: OPERATING MIPS VS. VOLTAGE Max MIPS Characteristic VDD Range (in Volts) — 3.0-3.6V(1) -40°C to +85°C 40 — 3.0-3.6V(1) -40°C to +125°C 40 Note 1: Temp Range (in °C) dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules such as the ADC, etc., will function but with degraded performance below VDDMIN.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Param Symbol No. Characteristic Min Typ(1) Max Units Conditions Operating Voltage DC10 VDD Supply Voltage(4) 3.0 — 3.6 V DC12 VDR RAM Data Retention Voltage(2) 1.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Parameter Typical(1) No. Max Units Conditions Operating Current (IDD)(2) DC20d 55 70 mA -40°C DC20a 55 70 mA +25°C 10 MIPS 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Parameter Typical(1) No. Max Units Conditions Operating Current (IDD)(2) DC27d 111 140 mA -40°C 40 MIPS DC27a 108 130 mA +25°C See Note 2, except PWM is 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Parameter No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Parameter No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Param Symbol No. VIL Characteristic Min Typ(1) Max Units Conditions Input Low Voltage DI10 I/O Pins VSS — 0.2 VDD V — DI15 MCLR VSS — 0.2 VDD V — DI16 I/O Pins with OSC1 VSS — 0.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Param Symbol No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Param. Symbol DO10 DO20 VOL VOH Characteristic Min. Typ. Max. Units Conditions Output Low Voltage I/O Pins: 4x Sink Driver Pins - RA0-RA2, RB0-RB2, RB5-RB10, RB15, RC1, RC2, RC9, RC10 — — 0.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-11: ELECTRICAL CHARACTERISTICS: BOR DC CHARACTERISTICS Param No. Symbol Standard Operating Conditions (see Note 3): 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Characteristic Min(1) Typ Max Units 2.55 — 2.79 V Conditions See Note 2 BO10 VBOR Note 1: 2: 3: Parameters are for design guidance only and are not tested in manufacturing.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-12: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended DC CHARACTERISTICS Param Symbol No. Characteristic Min Typ(1) Max 10,000 — — Units Conditions Program Flash Memory D130 EP Cell Endurance D131 VPR VDD for Read VMIN — 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 24.2 AC Characteristics and Timing Parameters This section defines dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 AC characteristics and timing parameters. TABLE 24-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Operating voltage VDD range as described in Table 24-1.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-2: EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 OS30 OS30 Q3 Q4 OSC1 OS20 OS31 OS31 OS25 CLKO OS41 OS40 TABLE 24-16: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V) AC CHARACTERISTICS Param No. Symbol Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Characteristic Min Typ(1) Max Units OS50 FPLLI PLL Voltage Controlled Oscillator (VCO) Input Frequency Range 0.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-19: AC CHARACTERISTICS: INTERNAL FRC ACCURACY AC CHARACTERISTICS Param No. Characteristic Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for Extended Min Typ Max Units Conditions Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1) F20a FRC -2 — +2 % -40°C ≤ TA ≤ +85°C VDD = 3.0-3.6V F20b FRC -5 — +5 % -40°C ≤ TA ≤ +125°C VDD = 3.0-3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-3: I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 24-1 for load conditions. TABLE 24-21: I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param No. Standard Operating Conditions: 3.0V to 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-4: VDD RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS SY12 MCLR SY10 Internal POR SY11 PWRT Time-out OSC Time-out SY30 Internal Reset Watchdog Timer Reset SY13 SY20 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure 24-1 for load conditions. © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-22: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param Symbol No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-5: TIMER1, 2 AND 3 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx11 Tx10 Tx15 OS60 Tx20 TMRx Note: Refer to Figure 24-1 for load conditions. TABLE 24-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-24: TIMER2 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ. Max.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-6: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC11 IC15 Note: Refer to Figure 24-1 for load conditions. TABLE 24-26: INPUT CAPTURE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-8: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA OC15 Active OCx Tri-state TABLE 24-28: SIMPLE OC/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-9: HIGH-SPEED PWM MODULE FAULT TIMING CHARACTERISTICS MP30 FLTx MP20 PWMx FIGURE 24-10: HIGH-SPEED PWM MODULE TIMING CHARACTERISTICS MP11 MP10 PWMx Note: Refer to Figure 24-1 for load conditions. TABLE 24-29: HIGH-SPEED PWM MODULE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-30: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY Standard Operating Conditions: 3.0V to 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-31: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-13: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = X, SMP = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx SP30, SP31 SP40 SDIx LSb MSb In LSb In Bit 14 - - - -1 SP41 Note: Refer to Figure 24-1 for load conditions. TABLE 24-32: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-14: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = X, SMP = 1) TIMING CHARACTERISTICS SCKx (CKP = 0) SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 SP30, SP31 SDIx MSb In LSb SP30, SP31 LSb In Bit 14 - - - -1 SP40 SP41 Note: Refer to Figure 24-1 for load conditions. TABLE 24-33: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-15: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDIx SDI MSb In Bit 14 - - - -1 SP51 LSb In SP41 SP40 Note: Refer to Figure 24-1 for load conditions. DS70318F-page 314 © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-34: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-16: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP52 SP50 SCKx (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 SP52 MSb SDOx Bit 14 - - - - - -1 LSb SP30,SP31 SDIx SDI MSb In Bit 14 - - - -1 SP51 LSb In SP41 SP40 Note: Refer to Figure 24-1 for load conditions. DS70318F-page 316 © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-35: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-17: SPIx SLAVE MODE (FULL-DUPLEX CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX Bit 14 - - - - - -1 LSb SP51 SP30,SP31 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 24-1 for load conditions. DS70318F-page 318 © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-36: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-18: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SSX SP52 SP50 SCKX (CKP = 0) SP70 SP73 SP72 SP72 SP73 SCKX (CKP = 1) SP35 MSb SDOX Bit 14 - - - - - -1 LSb SP51 SP30,SP31 SDIX MSb In Bit 14 - - - -1 LSb In SP41 SP40 Note: Refer to Figure 24-1 for load conditions. DS70318F-page 320 © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-37: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-19: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM34 IM30 IM33 SDAx Stop Condition Start Condition Note: Refer to Figure 24-1 for load conditions. FIGURE 24-20: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 SCLx IM11 IM26 IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 24-1 for load conditions. DS70318F-page 322 © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-38: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param Symbol No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 FIGURE 24-21: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS34 IS31 IS30 IS33 SDAx Stop Condition Start Condition FIGURE 24-22: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 SCLx IS30 IS26 IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out DS70318F-page 324 © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-39: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 = TABLE 24-40: 10-BIT HIGH-SPEED ADC MODULE SPECIFICATIONS Standard Operating Conditions (see Note2): 3.0V and 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param Symbol No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-41: 10-BIT HIGH-SPEED ADC MODULE TIMING REQUIREMENTS Standard Operating Conditions (see Note 2): 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended AC CHARACTERISTICS Param Symbol No. Characteristic Min. Typ(1) Max. Units Conditions — ns — Clock Parameters AD50b TAD ADC Clock Period AD55b tCONV Conversion Time AD56b FCNV Throughput Rate 35.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-42: COMPARATOR MODULE SPECIFICATIONS DC CHARACTERISTICS Standard Operating Conditions (see Note 2): 3.0V to 3.6V Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param. Symbol Characteristic No. Min Typ Max Units Comments CM10 VIOFF Input Offset Voltage -58 +14/-40 66 mV — CM11 VICM Input Common Mode Voltage Range(1) 0 — AVDD – 1.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 24-44: DAC OUTPUT BUFFER DC SPECIFICATIONS DC CHARACTERISTICS Standard Operating Conditions (see Note 1): 3.0V to 3.6V Operating temperature: -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param. Symbol Characteristic No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318F-page 330 © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 25.0 HIGH TEMPERATURE ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 electrical characteristics for devices operating in an ambient temperature range of -40°C to +150°C. Note: Programming of the Flash memory is not allowed above 125°C. The specifications between -40°C to +150°C are identical to those shown in Section 24.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 25.1 High Temperature DC Characteristics TABLE 25-1: OPERATING MIPS VS. VOLTAGE Max MIPS Characteristic VDD Range (in Volts) Temperature Range (in °C) — 3.0V to 3.6V(1) -40°C to +150°C Note 1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 20 Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules such as the ADC, etc., will function but with degraded performance below VDDMIN.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 25-4: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Power-Down Current (IPD)(2,4) HDC60e 1000 2000 μA +150°C 3.3V Base Power-Down Current HDC61c 100 110 μA +150°C 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 25-5: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature DC CHARACTERISTICS Param. Symbol DO10 DO20 VOL VOH Characteristic Min. Typ. Max. Units Conditions Output Low Voltage I/O Pins: 4x Sink Driver Pins - RA0-RA2, RB0-RB2, RB5-RB10, RB15, RC1, RC2, RC9, RC10 — — 0.4 V IOL ≤ 3.6 mA, VDD = 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 25-6: DC CHARACTERISTICS: PROGRAM MEMORY DC CHARACTERISTICS Param Symbol No. Characteristic(1) Standard Operating Conditions: 3.0V to 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 25.2 AC Characteristics and Timing Parameters The information contained in this section defines dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/ X04 AC characteristics and timing parameters for high temperature devices. However, all AC timing specifications in this section are the same as those in Section 31.2 “AC Characteristics and Timing Parameters”, with the exception of the parameters listed in this section.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 25-9: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Param No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 25-11: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) AC CHARACTERISTICS Operating temperature -40°C ≤ TA ≤ +150°C for High Temperature Param No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 26.0 50 MIPS ELECTRICAL CHARACTERISTICS This section provides an overview of dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 electrical characteristics for devices operating at 50 MIPS. The specifications for 50 MIPS are identical to those shown in Section 24.0 “Electrical Characteristics”, with the exception of the parameters listed in this section. Parameters in this section begin with the letter “M”, which denotes 50 MIPS operation.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 26.1 DC Characteristics TABLE 26-1: OPERATING MIPS VS. VOLTAGE Max MIPS Characteristic VDD Range (in Volts) Temp Range (in °C) — 3.0-3.6V(1) -40°C to +85°C Note 1: dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 50 Overall functional device operation at VBORMIN < VDD < VDDMIN is tested but not characterized. All device analog modules such as the ADC, etc., will function but with degraded performance below VDDMIN.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 26-3: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial DC CHARACTERISTICS Parameter No. Typical Max Units Conditions Idle Current (IIDLE): Core Off Clock On Base Current(1) MDC45d 64 105 mA -40°C MDC45a 64 105 mA +25°C MDC45b 64 105 mA +85°C Note 1: 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 26-4: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial DC CHARACTERISTICS Parameter No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 26.2 AC Characteristics and Timing Parameters This section defines dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 AC characteristics and timing parameters for 50 MIPS devices. TABLE 26-5: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 26-6: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param No. MTA10 Symbol TTXH Characteristic Min Typ Max Units Conditions TxCK High Synchronous, Time no prescaler TCY + 15 — — ns (TCY + 15)/N — — ns Asynchronous 15 — — ns Must also meet parameter TA15.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 26-7: TIMER2 EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param No.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE 26-9: SIMPLE OC/PWM MODE TIMING REQUIREMENTS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial AC CHARACTERISTICS Param No.
DC AND AC DEVICE CHARACTERISTICS GRAPHS Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. FIGURE 27-1: VOH – 4x DRIVER PINS -0.080 -0.030 3.6V -0.
FIGURE 27-6: VOL – 4x DRIVER PINS 0.120 0.040 0.035 3.6V 0.030 3.6V 0.100 3.3V 0.025 3.3V 0.080 3V IOL (A) IOL (A) VOL – 16x DRIVER PINS 0.020 0.015 Absolute Maximum 3V 0.060 Absolute Maximum 0.040 0.010 0.020 0.005 0.000 0.00 1.00 2.00 3.00 4.00 VOL (V) FIGURE 27-5: 0.060 3.6V 0.050 3.3V IOL (A) © 2008-2012 Microchip Technology Inc. 3V 0.030 Absolute Maximum 0.020 0.010 0.000 0.00 1.00 2.00 VOL (V) 1.00 2.00 VOL (V) VOL – 8x DRIVER PINS 0.040 0.000 0.00 3.00 4.
FIGURE 27-9: TYPICAL IPD CURRENT @ VDD = 3.3V 1220 118 108 1020 98 IDO OZE Current (mA) IPD Current (µA) TYPICAL IDOZE CURRENT @ VDD = 3.3V 820 620 420 88 78 68 50 MIPS 58 40 MIPS 48 38 220 28 20 -40 25 65 85 125 18 150 1:1 Temperature (Celsius) FIGURE 27-8: 1:2 1:64 1:128 Doze Ratio TYPICAL IDD CURRENT @ VDD = 3.3V FIGURE 27-10: 120 TYPICAL IIDLE CURRENT @ VDD = 3.
TYPICAL FRC FREQUENCY @ VDD = 3.3V FIGURE 27-13: 7.45 1.36 1.35 7.35 1.34 7.3 INTREF (V) FRC Frequency (MHz) 7.4 7.25 7.2 7.15 1.33 1.32 1.31 7.1 71 1.3 7.05 7 1.29 -40 25 85 125 150 FIGURE 27-12: TYPICAL LPRC FREQUENCY @ VDD = 3.3V 34 32 30 © 2008-2012 Microchip Technology Inc. 28 26 24 22 20 18 -40 25 85 Temperature (Celsius) -40 25 85 Temperature (Celsius) Temperature (Celsius) LPRC Frequency (kHz) TYPICAL INTREF @ VDD = 3.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 28.0 PACKAGING INFORMATION 28.1 Package Marking Information 18-Lead SOIC (.300”) Example XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX dsPIC33FJ06 GS101-I/SO YYWWNNN 0830235 e3 28-Lead SOIC Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SPDIP e3 * Note: 0830235 Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN Legend: XX...
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 28.1 Package Marking Information (Continued) 28-Lead QFN-S XXXXXXXX XXXXXXXX YYWWNNN 44-Lead QFN XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 33FJ06GS 202EMM e3 0830235 Example dsPIC33FJ16 GS504-E/ML e3 0830235 Example dsPIC33FJ 16GS504 -E/PT e3 0830235 44-Lead VTLA (TLA) Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN dsPIC33FJ 16GS504 e3 -E/TL Legend: XX...
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 28.
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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS70318F-page 362 © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318F-page 364 © 2008-2012 Microchip Technology Inc.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 APPENDIX A: REVISION HISTORY Revision A (January 2008) This is the initial revision of this document. Revision B (June 2008) This revision includes minor typographical and formatting changes throughout the data sheet text. In addition, redundant information was removed that is now available in the respective chapters of the dsPIC33F/PIC24H Family Reference Manual, which can be obtained from the Microchip website (www.microchip.com).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 7.0 “Oscillator Configuration” Update Description Removed the first sentence of the third clock source item (External Clock) in Section 7.1.1 “System Clock sources” Updated the default bit values for DOZE and FRCDIV in the Clock Divisor Register (see Register 7-2). Section 8.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 16.0 “Inter-Integrated Circuit (I2C™)” Update Description Removed the following sections, which are now available in the related section of the dsPIC33F/PIC24H Family Reference Manual: • 16.3 “I2C Interrupts” • 16.4 “Baud Rate Generator” (retained Figure 16-1: I2C Block Diagram) • 16.5 “I2C Module Addresses • 16.6 “Slave Address Masking” • 16.7 “IPMI Support” • 16.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-1: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 23.0 “Electrical Characteristics” Update Description Updated Typ values for Thermal Packaging Characteristics (Table 23-3). Removed Typ value for DC Temperature and Voltage Specifications parameter DC12 (Table 23-4). Updated all Typ values and conditions for DC Characteristics: Operating Current (IDD), updated last sentence in Note 2 (Table 23-5).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Revision C and D (March 2009) This revision includes minor typographical and formatting changes throughout the data sheet text. Global changes include: • Changed all instances of OSCI to OSC1 and OSCO to OSC2 • Changed all instances of PGCx/EMUCx and PGDx/EMUDx (where x = 1, 2, or 3) to PGECx and PGEDx • Changed all instances of VDDCORE and VDDCORE/ VCAP to VCAP/VDDCORE Other major changes are referenced by their respective section in the following table.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-2: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 8.0 “Oscillator Configuration” Update Description Added Note 2 to the Oscillator System Diagram (see Figure 8-1). Added a paragraph regarding FRC accuracy at the end of Section 8.1.1 “System Clock Sources”. Added Note 1 and Note 2 to the OSCON register (see Register ). Added Note 1 to the OSCTUN register (see Register 8-4). Added Note 3 to Section 8.4.2 “Oscillator Switching Sequence”.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-2: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 24.0 “Electrical Characteristics” Update Description Updated Typical values for Thermal Packaging Characteristics (see Table 24-3). Updated Min and Max values for parameter DC12 (RAM Data Retention Voltage) and added Note 4 (see Table 24-4). Updated Characteristics for I/O Pin Input Specifications (see Table 24-9). Added ISOURCE to I/O Pin Output Specifications (see Table 24-10).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Revision E (December 2009) The revision includes the following global update: • Added Note 2 to the shaded table that appears at the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits This revision also includes minor typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in the following table.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-3: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 21.0 “Special Features” Update Description Updated the second paragraph and removed the fourth paragraph in Section 21.1 “Configuration Bits”. Updated the Device Configuration Register Map (see Table 21-1). Section 24.0 “Electrical Characteristics” Updated the Absolute Maximum Ratings for high temperature and added Note 4. Updated Idle Current (IIDLE) Typical values in Table 24-6.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Revision F (January 2012) All occurrences of VDDCORE have been removed throughout the document. This revision also includes minor typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in the following table.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-4: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 24.0 “Electrical Characteristics” Update Description Updated the Absolute Maximum Ratings. Updated the Operating MIPS vs. Voltage (see Table 24-1). Updated parameter DC10 and Note 4, and removed parameter DC18 from the DC Temperature and Voltage Specifications (see Table 24-4). Updated Note 2 in the IDD Operating Current specification (see Table 24-5).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 TABLE A-4: MAJOR SECTION UPDATES (CONTINUED) Section Name Update Description Section 26.0 “50 MIPS Electrical Characteristics” Added new chapter in support of 50 MIPS devices. Section 27.0 “DC and AC Device Characteristics Graphs” Added new chapter. Section 28.0 “Packaging Information” Added 44-pin VTLA package marking information and diagrams (see Section 28.1 “Package Marking Information” and Section 28.2 “Package Details”, respectively).
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 INDEX A AC Characteristics ............................................ 298, 336, 343 Internal RC Accuracy ................................................ 301 Load Conditions ................................................ 298, 336 Alternate Vector Table (AIVT) ............................................. 95 Arithmetic Logic Unit (ALU)................................................. 35 Assembler MPASM Assembler................................................
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 Flexible Configuration ....................................................... 265 H High Temperature Electrical Characteristics..................... 331 High-Speed 10-bit Analog-to-Digital Converter (ADC)...... 237 High-Speed Analog Comparator ....................................... 261 High-Speed PWM ............................................................. 195 I I/O Ports ............................................................................
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 IEC1 (Interrupt Enable Control 1) ............................. 112 IEC3 (Interrupt Enable Control 3) ............................. 113 IEC4 (Interrupt Enable Control 4) ............................. 113 IEC5 (Interrupt Enable Control 5) ............................. 114 IFS0 (Interrupt Flag Status 0) ................................... 103 IFS1 (Interrupt Flag Status 1) ................................... 105 IFS3 (Interrupt Flag Status 3) .....................
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 OC/PWM ................................................................... 308 Output Compare (OCx) ............................................. 307 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer ................................................ 303 Timer1, 2, 3 External Clock....................................... 305 Timing Requirements External Clock ................................................... 299, 343 I/O ........................
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dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. dsPIC 33 FJ 06 GS1 02 T - 50 E / SP - XXX Examples: a) dsPIC33FJ06GS102-E/SP: SMPS dsPIC33, 6-Kbyte program memory, 28-pin, Extended temperature, SPDIP package.
dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 NOTES: DS70318F-page 384 © 2008-2012 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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