Specifications

Section 16. Analog-to-Digital Converter (ADC)

16.22 OPERATION DURING SLEEP AND IDLE MODES

Sleep and Idle modes are useful for minimizing conversion noise because the digital activity of

the CPU, buses and other peripherals is minimized.

16.22.1 CPU Sleep Mode without RC A/D Clock

When the device enters Sleep mode, all clock sources to the ADC module are shut down and

stay at logic ‘0’.

If Sleep occurs in the middle of a conversion, the conversion is aborted unless the ADC is

clocked from its internal RC clock generator. The converter does not resume a partially com-

pleted conversion on exiting from Sleep mode.

16.22.2 CPU Sleep Mode with RC A/D Clock

The ADC module can operate during Sleep mode if the A/D clock source is set to the internal A/D

RC oscillator (ADRC = 1). This eliminates digital switching noise from the conversion. When the

conversion is completed, the DONE bit is set and the result is loaded into the ADC Result buffer,

ADCBUF.

If the ADC interrupt is enabled (ADxIE = 1), the device wakes up from Sleep when the ADC

interrupt occurs. Program execution resumes at the ADC Interrupt Service Routine if the ADC

interrupt is greater than the current CPU priority. Otherwise, execution continues from the

instruction after the PWRSAV instruction that placed the device in Sleep mode.

If the ADC interrupt is not enabled, the ADC module is turned off, although the ADON bit remains

set.

To minimize the effects of digital noise on the ADC module operation, the user should select a

conversion trigger source that ensures the A/D conversion will take place in Sleep mode. The

automatic conversion trigger option can be used for sampling and conversion in Sleep

(SSRC<2:0> = 111). To use the automatic conversion option, the ADON bit should be set in the

instruction before the PWRSAV instruction.

16.22.3 ADC Operation During CPU Idle Mode

For the A/D conversion, the ADSIDL bit (ADxCON1<13>) selects if the ADC module stops or con-

tinues on Idle. If ADSIDL = 0, the ADC module continues normal operation when the device

enters Idle mode. If the ADC interrupt is enabled (ADxIE = 1), the device wakes up from Idle

mode when the ADC interrupt occurs. Program execution resumes at the ADC Interrupt Service

Routine if the ADC interrupt is greater than the current CPU priority. Otherwise, execution con-

tinues from the instruction after the PWRSAV instruction that placed the device in Idle mode.

If ADSIDL = 1, the ADC module stops in Idle. If the device enters Idle mode in the middle of a

conversion, the conversion is aborted. The converter does not resume a partially completed

conversion on exiting from Idle mode.

Note: For the ADC module to operate in Sleep, the ADC clock source must be set to RC

(ADRC = 1).